Change in coreboot[master]: soc/intel/alderlake: add processor power limits control support

[Furquan Shaikh (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Sumeet R Pawnikar, Patrick Rudolph.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51397 )

Change subject: soc/intel/alderlake: add processor power limits control support
......................................................................

Patch Set 1:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/51397/comment/9b4f2ffa_df6944da 
PS1, Line 14: test
> Verified these PL1 and PL2 values using corbeoot logs.

Ack. Can you please add that to the commit message?

File src/soc/intel/alderlake/systemagent.c:

https://review.coreboot.org/c/coreboot/+/51397/comment/9318a2bf_403e2c0f 
PS1, Line 63: Configure turbo power limits 1ms after reset complete bit
> This delay time is coming as legacy on IA. […]

Strange. I don't see mention of the 1ms delay required between setting of CPL and configuring of turbo power limits in the EDS. What version of the EDS are you looking at? And what is the relevant section #?