Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38016 )
Change subject: Documentation/superio: add generic PNP device documentation ......................................................................
Documentation/superio: add generic PNP device documentation
Change-Id: Iee75faaef713dd6ec6b6e2d536df09a41010eebf Signed-off-by: Felix Held felix-coreboot@felixheld.de --- A Documentation/superio/common/pnp.md M Documentation/superio/index.md 2 files changed, 68 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/38016/1
diff --git a/Documentation/superio/common/pnp.md b/Documentation/superio/common/pnp.md new file mode 100644 index 0000000..f1e97bc --- /dev/null +++ b/Documentation/superio/common/pnp.md @@ -0,0 +1,67 @@ +# PNP devices + +Typical PNP devices are super I/Os, LPC-connected TPMs and board management controllers. + +PNP devices are usually connected to the LPC bus of a system and shouldn't be confused with PCI(e) devices that use a completely different plug and play mechanism. +PNP originates in the ISA plug and play specification. Since the original ISA bus is more or less extinct, the auto-detection part of ISA PNP is mostly irrelevant nowadays. +For the register offsets for different functionality, appendix A of that specification is still the main reference though. + +## configuration access and config mode + +Super I/O chips connected via LPC to the southbridge usually have their I/O-mapped configuration interface with a size of two bytes at the base address 0x2e or 0x4e. +Other PNP devices have their configuration interface at other addresses. + +The two byte registers allow access to an indirect 256 bytes big register space that contains the configuration. By writing the index to the lower byte (e.g. 0x2e), you can access the register contents at that index by reading/writing the higher byte (e.g. 0x2f). + +To prevent accicdental changes of the super I/O (SIO) configuration, the SIOs need a configuraton mode unlock sequence. After changing the configuration, the configuratuon mode should be left again, by sending the configuration mode lock sequence. + +## logical device numbers (LDN) + +Each PNP device can contain multiple logical devices. +The bytes from 0x00 to 0x2f in the indirect configuration register space are common for all LDNs, but some SIO chips require a certain LDN to be selected in order to write certain registers in there. +An LDN gets selected by writing the LDN number to the LDN select register 0x07. +Registers 0x30 to 0xFF are specific to each LDN number. + +coreboot encodes the physical LDN number in the lower byte of the LDN number. + +### vitual logical device numbers + +Register 0x30 is the LDN enable register and since it is an 8 bit register, it can contain up to 8 enable bits for different parts of the functionality of that logical device. +To set a certain enable bit in one physical LDN, the concept of virtual LDNs was introduced. +Virtual LDNs share the registers of their base LDN, but allow to specify which part of a LDN should be enabled. + +coreboot encodes the enable bit number and by that the virtual LDN part in the lower 3 bits of the higher byte of the LDN number. + +## I/O resources + +Starting at register address 0x60, each LDN has 2 byte wide I/O base address registers. +The size of of an I/O resource is always a power of two. + +### I/O resource masks + +The I/O resource masks encode both the size and the maximum base address of the corresponding IO resource. +The number of zeros counted from the least significant bit encode the resource size. If N is the number of LSBs being zero, which can also be zero if the LSB is a one, the resource has N address bits and a size of 2**N bytes. The mask address is also the highest possible address to map the I/O region. + +A typical example for an I/O resource mask is 0x07f8 which is 0b0000011111111000 in binary notation. +There the three LSBs are zeros here, so it's an eight byte I/O resource with three address offset bits inside the resource. +The highest base address it can be mapped to is 0x07f8, so the region will end at 0x07ff. + +The super I/O datasheets typically contain the information about the I/O resource masks. +On most super I/O chips the mask can also be found out by writing 0xffff to the corresponding I/O base address register and reading back the value; since the lowest and highest bits are hard-wired to zero according to the I/O resource size and maximal possible I/O address, this gives the mask. + +## IRQ resources + +Each physical LDN has up to two configurable interrupt request register pairs 0x70, 0x71 and 0x72, 0x73. +The first register selects the IRQ number from 1 to 15 and 0 deactivated the corresponding IRQ. The second register selects the IRQ type (level or edge) and IRQ level (high or low). + +On the LPC bus a shared SERIRQ line is used to signal IRQs to the host; the IRQ number gets encoded by the number of LPC clock cycles after the start frame before the device pulls the open drain connection low. + +SERIRQ can be used in two different modes: +In the continous SERIRQ mode the host continuously sends IRQ frame starts and the devices signal and devices signal their IRQ request by pulling low the SERIRQ line at the right time. +In quiet SERIRQ mode the host doesn't send IRQ frame starts, so the devices have to send both the IRQ frame start and the encoded IRQ number. +The quiet mode is often broken. + +## DRQ resources + +Each physical LDN has two legacy ISA-style DMA request channel registers at 0x74 and 0x75. +Those are only used for legacy devices like parallel printer ports or floppy disk controllers. diff --git a/Documentation/superio/index.md b/Documentation/superio/index.md index 39965fd..053663b 100644 --- a/Documentation/superio/index.md +++ b/Documentation/superio/index.md @@ -7,4 +7,5 @@ - [NPCD378](nuvoton/npcd378.md)
## Common +- [PNP devices](common/pnp.md) - [SSDT generator for generic SuperIOs](common/ssdt.md)
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38016 )
Change subject: Documentation/superio: add generic PNP device documentation ......................................................................
Patch Set 1:
(5 comments)
https://review.coreboot.org/c/coreboot/+/38016/1/Documentation/superio/commo... File Documentation/superio/common/pnp.md:
https://review.coreboot.org/c/coreboot/+/38016/1/Documentation/superio/commo... PS1, Line 27: ### vitual logical device numbers vital or virtual :)
https://review.coreboot.org/c/coreboot/+/38016/1/Documentation/superio/commo... PS1, Line 33: coreboot encodes the enable bit number and by that the virtual LDN part in the lower 3 bits of the higher byte of the LDN number. This is true, while confusing. I think we should do a somewhat major redesign on the devicetree.cb, possibly taking advantage of override trees to reduce the amount of code duplication we have for super-ios.
https://review.coreboot.org/c/coreboot/+/38016/1/Documentation/superio/commo... PS1, Line 55: The first register selects the IRQ number from 1 to 15 and 0 deactivated the corresponding IRQ. The second register selects the IRQ type (level or edge) and IRQ level (high or low). IRQ type is not really something configurable? HOST expects edge triggered SERIRQ?
The topic on IRQ routing and PIC/IOAPIC/MSI/MSI-X would be a completely separate document to cover.
https://review.coreboot.org/c/coreboot/+/38016/1/Documentation/superio/commo... PS1, Line 60: In the continous SERIRQ mode the host continuously sends IRQ frame starts and the devices signal and devices signal their IRQ request by pulling low the SERIRQ line at the right time. extra 'and devices signal'
https://review.coreboot.org/c/coreboot/+/38016/1/Documentation/superio/commo... PS1, Line 67: Those are only used for legacy devices like parallel printer ports or floppy disk controllers. Support for DRQ on the host side may have been dropped with recent chipsets.
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Change subject: Documentation/superio: add generic PNP device documentation ......................................................................
Documentation/superio: add generic PNP device documentation
Change-Id: Iee75faaef713dd6ec6b6e2d536df09a41010eebf Signed-off-by: Felix Held felix-coreboot@felixheld.de --- A Documentation/superio/common/pnp.md M Documentation/superio/index.md 2 files changed, 72 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/38016/2
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38016 )
Change subject: Documentation/superio: add generic PNP device documentation ......................................................................
Patch Set 2:
(5 comments)
https://review.coreboot.org/c/coreboot/+/38016/1/Documentation/superio/commo... File Documentation/superio/common/pnp.md:
https://review.coreboot.org/c/coreboot/+/38016/1/Documentation/superio/commo... PS1, Line 27: ### vitual logical device numbers
vital or virtual :)
Done
https://review.coreboot.org/c/coreboot/+/38016/1/Documentation/superio/commo... PS1, Line 33: coreboot encodes the enable bit number and by that the virtual LDN part in the lower 3 bits of the higher byte of the LDN number.
This is true, while confusing. I think we should do a somewhat major redesign on the devicetree. […]
I'm currently trying to document the current state and how to use that. I don't think that the current state is too bad though here.
https://review.coreboot.org/c/coreboot/+/38016/1/Documentation/superio/commo... PS1, Line 55: The first register selects the IRQ number from 1 to 15 and 0 deactivated the corresponding IRQ. The second register selects the IRQ type (level or edge) and IRQ level (high or low).
IRQ type is not really something configurable? HOST expects edge triggered SERIRQ? […]
Haven't found the corresponding spec, but all LPC SIO datasheets/documentation I found used edge type irqs and don't have the register documented/writeable.
I don't want to dive deep into IRQ routing here, but only document the LPC PNP stuff.
https://review.coreboot.org/c/coreboot/+/38016/1/Documentation/superio/commo... PS1, Line 60: In the continous SERIRQ mode the host continuously sends IRQ frame starts and the devices signal and devices signal their IRQ request by pulling low the SERIRQ line at the right time.
extra 'and devices signal'
Done
https://review.coreboot.org/c/coreboot/+/38016/1/Documentation/superio/commo... PS1, Line 67: Those are only used for legacy devices like parallel printer ports or floppy disk controllers.
Support for DRQ on the host side may have been dropped with recent chipsets.
Done
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38016 )
Change subject: Documentation/superio: add generic PNP device documentation ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38016/2/Documentation/superio/commo... File Documentation/superio/common/pnp.md:
https://review.coreboot.org/c/coreboot/+/38016/2/Documentation/superio/commo... PS2, Line 16: configuraton configuration
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I'd like you to reexamine a change. Please visit
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Change subject: Documentation/superio: add generic PNP device documentation ......................................................................
Documentation/superio: add generic PNP device documentation
Change-Id: Iee75faaef713dd6ec6b6e2d536df09a41010eebf Signed-off-by: Felix Held felix-coreboot@felixheld.de --- A Documentation/superio/common/pnp.md M Documentation/superio/index.md 2 files changed, 72 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/38016/3
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38016 )
Change subject: Documentation/superio: add generic PNP device documentation ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38016/2/Documentation/superio/commo... File Documentation/superio/common/pnp.md:
https://review.coreboot.org/c/coreboot/+/38016/2/Documentation/superio/commo... PS2, Line 16: configuraton
configuration
Done
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38016 )
Change subject: Documentation/superio: add generic PNP device documentation ......................................................................
Patch Set 3: Code-Review+1
(3 comments)
https://review.coreboot.org/c/coreboot/+/38016/3/Documentation/superio/commo... File Documentation/superio/common/pnp.md:
https://review.coreboot.org/c/coreboot/+/38016/3/Documentation/superio/commo... PS3, Line 38: of of of
https://review.coreboot.org/c/coreboot/+/38016/3/Documentation/superio/commo... PS3, Line 46: There redundant with "here" later in the sentence.
https://review.coreboot.org/c/coreboot/+/38016/3/Documentation/superio/commo... PS3, Line 55: The first register selects the IRQ number from 1 to 15 and 0 deactivated the corresponding IRQ. That took me three attempts until I understood what you mean. Maybe something like: "Each pair can be configured to use a certain interrupt ID. Writing 1 to 15 into the first register enables using that IRQ# while 0 disables it."?
Hello build bot (Jenkins), Patrick Georgi,
I'd like you to reexamine a change. Please visit
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Change subject: Documentation/superio: add generic PNP device documentation ......................................................................
Documentation/superio: add generic PNP device documentation
Change-Id: Iee75faaef713dd6ec6b6e2d536df09a41010eebf Signed-off-by: Felix Held felix-coreboot@felixheld.de --- A Documentation/superio/common/pnp.md M Documentation/superio/index.md 2 files changed, 73 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/38016/4
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38016 )
Change subject: Documentation/superio: add generic PNP device documentation ......................................................................
Patch Set 3:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38016/3/Documentation/superio/commo... File Documentation/superio/common/pnp.md:
https://review.coreboot.org/c/coreboot/+/38016/3/Documentation/superio/commo... PS3, Line 38: of of
of
Done
https://review.coreboot.org/c/coreboot/+/38016/3/Documentation/superio/commo... PS3, Line 46: There
redundant with "here" later in the sentence.
Done
https://review.coreboot.org/c/coreboot/+/38016/3/Documentation/superio/commo... PS3, Line 55: The first register selects the IRQ number from 1 to 15 and 0 deactivated the corresponding IRQ.
That took me three attempts until I understood what you mean. […]
Done
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38016 )
Change subject: Documentation/superio: add generic PNP device documentation ......................................................................
Patch Set 4: Code-Review+1
(4 comments)
https://review.coreboot.org/c/coreboot/+/38016/4/Documentation/superio/commo... File Documentation/superio/common/pnp.md:
https://review.coreboot.org/c/coreboot/+/38016/4/Documentation/superio/commo... PS4, Line 3: super Super
https://review.coreboot.org/c/coreboot/+/38016/4/Documentation/superio/commo... PS4, Line 5: PNP devices are usually connected to the LPC bus of a system and shouldn't be confused with PCI(e) devices that use a completely different plug and play mechanism. I wouldn’t break the line after each sentence, end also adhere to the line length limit.
https://review.coreboot.org/c/coreboot/+/38016/4/Documentation/superio/commo... PS4, Line 6: ISA plug and play specification Add an URL?
https://review.coreboot.org/c/coreboot/+/38016/4/Documentation/superio/commo... PS4, Line 9: ## configuration access and config mode Start headings with capital letter?
Hello Angel Pons, Paul Menzel, build bot (Jenkins), Patrick Georgi,
I'd like you to reexamine a change. Please visit
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Change subject: Documentation/superio: add generic PNP device documentation ......................................................................
Documentation/superio: add generic PNP device documentation
Change-Id: Iee75faaef713dd6ec6b6e2d536df09a41010eebf Signed-off-by: Felix Held felix-coreboot@felixheld.de --- A Documentation/superio/common/pnp.md M Documentation/superio/index.md 2 files changed, 96 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/38016/5
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38016 )
Change subject: Documentation/superio: add generic PNP device documentation ......................................................................
Patch Set 5:
(4 comments)
https://review.coreboot.org/c/coreboot/+/38016/4/Documentation/superio/commo... File Documentation/superio/common/pnp.md:
https://review.coreboot.org/c/coreboot/+/38016/4/Documentation/superio/commo... PS4, Line 3: super
Super
Done
https://review.coreboot.org/c/coreboot/+/38016/4/Documentation/superio/commo... PS4, Line 5: PNP devices are usually connected to the LPC bus of a system and shouldn't be confused with PCI(e) devices that use a completely different plug and play mechanism.
I wouldn’t break the line after each sentence, end also adhere to the line length limit.
Done. reflowed the text to 96 chars per line
https://review.coreboot.org/c/coreboot/+/38016/4/Documentation/superio/commo... PS4, Line 6: ISA plug and play specification
Add an URL?
URLs break from time to time; if the document had a document id, i'd have that added here, but it doesn't
https://review.coreboot.org/c/coreboot/+/38016/4/Documentation/superio/commo... PS4, Line 9: ## configuration access and config mode
Start headings with capital letter?
Done
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38016 )
Change subject: Documentation/superio: add generic PNP device documentation ......................................................................
Patch Set 5: Code-Review+1
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38016 )
Change subject: Documentation/superio: add generic PNP device documentation ......................................................................
Patch Set 5:
(4 comments)
https://review.coreboot.org/c/coreboot/+/38016/4/Documentation/superio/commo... File Documentation/superio/common/pnp.md:
https://review.coreboot.org/c/coreboot/+/38016/4/Documentation/superio/commo... PS4, Line 5: PNP devices are usually connected to the LPC bus of a system and shouldn't be confused with PCI(e) devices that use a completely different plug and play mechanism.
Done. […]
According to https://doc.coreboot.org/getting_started/writing_documentation.html the line length is 72.
https://review.coreboot.org/c/coreboot/+/38016/5/Documentation/superio/commo... File Documentation/superio/common/pnp.md:
https://review.coreboot.org/c/coreboot/+/38016/5/Documentation/superio/commo... PS5, Line 5: LPC or eSPI
https://review.coreboot.org/c/coreboot/+/38016/5/Documentation/superio/commo... PS5, Line 21: super Super, same below
https://review.coreboot.org/c/coreboot/+/38016/5/Documentation/superio/commo... PS5, Line 28: allLDNs space
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38016 )
Change subject: Documentation/superio: add generic PNP device documentation ......................................................................
Patch Set 5:
(4 comments)
https://review.coreboot.org/c/coreboot/+/38016/4/Documentation/superio/commo... File Documentation/superio/common/pnp.md:
https://review.coreboot.org/c/coreboot/+/38016/4/Documentation/superio/commo... PS4, Line 5: PNP devices are usually connected to the LPC bus of a system and shouldn't be confused with PCI(e) devices that use a completely different plug and play mechanism.
According to https://doc.coreboot.org/getting_started/writing_documentation. […]
Done.
I asked in the leadership meeting what the rationale for the 72 chars per line vs. the 96 for code was; for code it's more, since the code usually has 2 levels of indentation on average, but the documentation not.
https://review.coreboot.org/c/coreboot/+/38016/5/Documentation/superio/commo... File Documentation/superio/common/pnp.md:
https://review.coreboot.org/c/coreboot/+/38016/5/Documentation/superio/commo... PS5, Line 5: LPC
or eSPI
Done
https://review.coreboot.org/c/coreboot/+/38016/5/Documentation/superio/commo... PS5, Line 21: super
Super, same below
Done
https://review.coreboot.org/c/coreboot/+/38016/5/Documentation/superio/commo... PS5, Line 28: allLDNs
space
Done
Hello Angel Pons, Paul Menzel, build bot (Jenkins), Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38016
to look at the new patch set (#6).
Change subject: Documentation/superio: add generic PNP device documentation ......................................................................
Documentation/superio: add generic PNP device documentation
Change-Id: Iee75faaef713dd6ec6b6e2d536df09a41010eebf Signed-off-by: Felix Held felix-coreboot@felixheld.de --- A Documentation/superio/common/pnp.md M Documentation/superio/index.md 2 files changed, 115 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/38016/6
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38016 )
Change subject: Documentation/superio: add generic PNP device documentation ......................................................................
Patch Set 6: Code-Review+1
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38016 )
Change subject: Documentation/superio: add generic PNP device documentation ......................................................................
Patch Set 6: Code-Review+2
You could make more use of markdowns highlighting capabilities, but the information itself is fine.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38016 )
Change subject: Documentation/superio: add generic PNP device documentation ......................................................................
Patch Set 6:
You could make more use of markdowns highlighting capabilities, but the information itself is fine.
I'll look into that and do that as a follow-up patch
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38016 )
Change subject: Documentation/superio: add generic PNP device documentation ......................................................................
Documentation/superio: add generic PNP device documentation
Change-Id: Iee75faaef713dd6ec6b6e2d536df09a41010eebf Signed-off-by: Felix Held felix-coreboot@felixheld.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/38016 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Patrick Rudolph siro@das-labor.org --- A Documentation/superio/common/pnp.md M Documentation/superio/index.md 2 files changed, 115 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Patrick Rudolph: Looks good to me, approved
diff --git a/Documentation/superio/common/pnp.md b/Documentation/superio/common/pnp.md new file mode 100644 index 0000000..314cac2 --- /dev/null +++ b/Documentation/superio/common/pnp.md @@ -0,0 +1,114 @@ +# PNP devices + +Typical PNP devices are Super I/Os, LPC-connected TPMs and board +management controllers. + +PNP devices are usually connected to the LPC or eSPI bus of a system +and shouldn't be confused with PCI(e) devices that use a completely +different plug and play mechanism. PNP originates in the ISA plug and +play specification. Since the original ISA bus is more or less extinct, +the auto-detection part of ISA PNP is mostly irrelevant nowadays. For +the register offsets for different functionality, appendix A of that +specification is still the main reference though. + +## Configuration access and config mode + +Super I/O chips connected via LPC to the southbridge usually have their +I/O-mapped configuration interface with a size of two bytes at the base +address 0x2e or 0x4e. Other PNP devices have their configuration +interface at other addresses. + +The two byte registers allow access to an indirect 256 bytes big +register space that contains the configuration. By writing the index +to the lower byte (e.g. 0x2e), you can access the register contents at +that index by reading/writing the higher byte (e.g. 0x2f). + +To prevent accidental changes of the Super I/O (SIO) configuration, +the SIOs need a configuration mode unlock sequence. After changing the +configuration, the configuration mode should be left again, by sending +the configuration mode lock sequence. + +## Logical device numbers (LDN) + +Each PNP device can contain multiple logical devices. The bytes from +0x00 to 0x2f in the indirect configuration register space are common +for all LDNs, but some SIO chips require a certain LDN to be selected +in order to write certain registers in there. An LDN gets selected by +writing the LDN number to the LDN select register 0x07. Registers 0x30 +to 0xFF are specific to each LDN number. + +coreboot encodes the physical LDN number in the lower byte of the LDN +number. + +### Virtual logical device numbers + +Register 0x30 is the LDN enable register and since it is an 8 bit +register, it can contain up to 8 enable bits for different parts of +the functionality of that logical device. To set a certain enable bit +in one physical LDN, the concept of virtual LDNs was introduced. +Virtual LDNs share the registers of their base LDN, but allow to +specify which part of a LDN should be enabled. + +coreboot encodes the enable bit number and by that the virtual LDN +part in the lower 3 bits of the higher byte of the LDN number. + +## I/O resources + +Starting at register address 0x60, each LDN has 2 byte wide I/O base +address registers. The size of an I/O resource is always a power of +two. + +### I/O resource masks + +The I/O resource masks encode both the size and the maximum base +address of the corresponding IO resource. The number of zeros counted +from the least significant bit encode the resource size. If N is the +number of LSBs being zero, which can also be zero if the LSB is a one, +the resource has N address bits and a size of 2**N bytes. The mask +address is also the highest possible address to map the I/O region. + +A typical example for an I/O resource mask is 0x07f8 which is +0b0000011111111000 in binary notation. The three LSBs are zeros here, +so it's an eight byte I/O resource with three address offset bits +inside the resource. The highest base address it can be mapped to is +0x07f8, so the region will end at 0x07ff. + +The Super I/O datasheets typically contain the information about the +I/O resource masks. On most Super I/O chips the mask can also be found +out by writing 0xffff to the corresponding I/O base address register +and reading back the value; since the lowest and highest bits are +hard-wired to zero according to the I/O resource size and maximal +possible I/O address, this gives the mask. + +## IRQ resources + +Each physical LDN has up to two configurable interrupt request +register pairs 0x70, 0x71 and 0x72, 0x73. Each pair can be configured +to use a certain IRQ number. Writing 1 to 15 into the first register +selects the IRQ number generated by the corresponding IRQ source and +enables IRQ generation; writing 0 to it disables the generation of +IRQs for the source. The second register selects the IRQ type (level +or edge) and IRQ level (high or low). For LPC SIOs the IRQ type is +hard-wired to edge. + +On the LPC bus a shared SERIRQ line is used to signal IRQs to the +host; the IRQ number gets encoded by the number of LPC clock cycles +after the start frame before the device pulls the open drain +connection low. + +SERIRQ can be used in two different modes: In the continuous SERIRQ +mode the host continuously sends IRQ frame starts and the devices +signal their IRQ request by pulling low the SERIRQ line at the right +time. In quiet SERIRQ mode the host doesn't send IRQ frame starts, so +the devices have to send both the IRQ frame start and the encoded IRQ +number. The quiet mode is often broken. + +## DRQ resources + +Each physical LDN has two legacy ISA-style DMA request channel +registers at 0x74 and 0x75. Those are only used for legacy devices +like parallel printer ports or floppy disk controllers. + +Each device using LPC legacy DMA needs its own LDMA line to the host. +Some newer chipsets have dropped the LDMA line and with that the +legacy DMA capability on LPC. diff --git a/Documentation/superio/index.md b/Documentation/superio/index.md index 39965fd..053663b 100644 --- a/Documentation/superio/index.md +++ b/Documentation/superio/index.md @@ -7,4 +7,5 @@ - [NPCD378](nuvoton/npcd378.md)
## Common +- [PNP devices](common/pnp.md) - [SSDT generator for generic SuperIOs](common/ssdt.md)
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Felix Held (Code Review) -
HAOUAS Elyes (Code Review)
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Kyösti Mälkki (Code Review)
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Patrick Georgi (Code Review)
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Patrick Rudolph (Code Review)
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Paul Menzel (Code Review)