Attention is currently required from: Angel Pons, Bill XIE, Nicholas Chin.
Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email )
Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes ......................................................................
Patch Set 7:
(1 comment)
File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c:
https://review.coreboot.org/c/coreboot/+/85413/comment/4f30c54b_baa89725?usp... : PS7, Line 104: 0x40
No, those values are from digging through p8z77-v vendor bios, module PcieLaneDxe, with Ghidra. […]
Bill, if you have a multimeter on hand, this next test will settle everything once and for all (I hope).
I'd like you to probe the three PCIe switcher select signals directly, while running vendor BIOS, for each possible setting - start with the one where PCIEX1_2 actually works. You need not boot any OS at all, though it shouldn't hurt. Hook the meter's negative lead to a ground and use the positive lead to probe these three locations:
X_QSW_SEL2: QSWR504 pad 2 (towards the PCI slot) X_QSW_SEL3: QSWR504 pad 1 (towards the PCIEX16_1 slot) X_QSW_SEL4: QSWQ7 pin 3 (on the single leg side)
QSWR504 according to boardview should be unpopulated, giving you access to both pads.
I uploaded a map of their positions on the board to the issue tracker.
High is 3.3v.
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Keith Hui (Code Review)