[S] Change in coreboot[main]: vendorcode/amd/opensil: Implement cbmem_top_chipset - coreboot-gerrit

29 Nov 2023


      Attention is currently required from: Arthur Heymans, Martin L Roth.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76513?usp=email )
Change subject: vendorcode/amd/opensil: Implement cbmem_top_chipset
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Patch Set 6:
(1 comment)
File src/vendorcode/amd/opensil/genoa_poc/romstage.c:
https://review.coreboot.org/c/coreboot/+/76513/comment/342ac756_32ea74e7 :
PS6, Line 16: top_mem
...
i'd replace this with top_mem - CONFIG_SMM_TSEG_SIZE and drop line 14. […]
solved this a bit differently by moving top_mem -= CONFIG_SMM_TSEG_SIZE into the if (CONFIG_SMM_TSEG_SIZE) block
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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I269663414f4d8e39eb218cd6348bfce7989a79f9
Gerrit-Change-Number: 76513
Gerrit-PatchSet: 6
Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz
Gerrit-Reviewer: Martin L Roth gaumless@gmail.com
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