Change in coreboot[master]: soc/intel/common/block/irq: Add support for intel_write_pci0_PRT

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Nico Huber, Furquan Shaikh, Patrick Rudolph.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51159 )

Change subject: soc/intel/common/block/irq: Add support for intel_write_pci0_PRT
......................................................................

Patch Set 7:

(1 comment)

File src/soc/intel/common/block/irq/irq.c:

https://review.coreboot.org/c/coreboot/+/51159/comment/4508ff45_f1b3e5a8 
PS7, Line 378: 		/* Map INTA->PIRQ_A, INTB->PIRQ_B, INTC->PIRQ_C, INTD->PIRQ_D */
> This is tying a knot in my head... it can only be true for […]

Sorry I can make the comment a little more clear, this is how Intel does the mapping for PIC-mode IRQs (IRQ11 for INTA,INTC,INTD, and IRQ10 for INTB).

Take another look at the CB:50857, `pic_pirq` is eventually used as an index into `pirq_map->{gsi,source_path}` for the PIC-mode table. The global_least_used_pirq is used for APIC-mode.

However, about your theory, I think that it is valid, I have not 100% confirmed it, but I believe that the "unique IRQ" devices just won't work correctly in legacy mode.

The only reason I know of that anyone would care about the PIC-mode IRQs is for, e.g., testing `noapic` in Linux? I really don't know of a good argument to keep the legacy PIC mappings around anymore... not for this patch, but should be investigated and possibly removed if it's just not useful anymore.