Change in ...coreboot[master]: mb/google/sarien/variants/sarien: Set PCH Thermal Trip point to 75 de...
Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33131
Change subject: mb/google/sarien/variants/sarien: Set PCH Thermal Trip point to 75 degree C ......................................................................
mb/google/sarien/variants/sarien: Set PCH Thermal Trip point to 75 degree C
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal Shutdown when S0ix is enabled.
BUG=None BRANCH=None TEST=Verified Thermal Device (B0: D20: F2) TSPM offset 0x1c [LTT (8:0)] value is 0xFA.
Change-Id: Ibc336be0523ff4e65a818474907faf20fc417ff4 Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/sarien/variants/sarien/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/33131/1
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index c96423c..595fcf5 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -163,6 +163,9 @@
register "tcc_offset" = "10"
+ # PCH Trip Temperature in degree C + register "pch_trip_temp" = "75" + register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = {
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33131 )
Change subject: mb/google/sarien/variants/sarien: Set PCH Thermal Trip point to 75 degree C ......................................................................
Patch Set 1:
This CL depends on https://review.coreboot.org/c/coreboot/+/33129
Hello Aaron Durbin, Duncan Laurie, build bot (Jenkins), Furquan Shaikh, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33131
to look at the new patch set (#3).
Change subject: mb/google/sarien/variants/sarien: Set PCH Thermal Trip point to 77 degree C ......................................................................
mb/google/sarien/variants/sarien: Set PCH Thermal Trip point to 77 degree C
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal Shutdown when S0ix is enabled.
BUG=None BRANCH=None TEST=Verified Thermal Device (B0: D20: F2) TSPM offset 0x1c [LTT (8:0)] value is 0xFA.
Change-Id: Ibc336be0523ff4e65a818474907faf20fc417ff4 Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/sarien/variants/sarien/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/33131/3
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33131 )
Change subject: mb/google/sarien/variants/sarien: Set PCH Thermal Trip point to 77 degree C ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/33131/3/src/mainboard/google/sarien... File src/mainboard/google/sarien/variants/sarien/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/33131/3/src/mainboard/google/sarien... PS3, Line 228: device pci 12.0 on end # Thermal Subsystem place under thermal device
Hello Aaron Durbin, Duncan Laurie, build bot (Jenkins), Furquan Shaikh, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33131
to look at the new patch set (#4).
Change subject: mb/google/sarien/variants/sarien: Set PCH Thermal Trip point to 77 degree C ......................................................................
mb/google/sarien/variants/sarien: Set PCH Thermal Trip point to 77 degree C
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal Shutdown when S0ix is enabled.
BUG=None BRANCH=None TEST=Verified Thermal Device (B0: D20: F2) TSPM offset 0x1c [LTT (8:0)] value is 0xFE on Sarien.
Change-Id: Ibc336be0523ff4e65a818474907faf20fc417ff4 Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/sarien/variants/sarien/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/33131/4
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33131 )
Change subject: mb/google/sarien/variants/sarien: Set PCH Thermal Trip point to 77 degree C ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/33131/3/src/mainboard/google/sarien... File src/mainboard/google/sarien/variants/sarien/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/33131/3/src/mainboard/google/sarien... PS3, Line 228: device pci 12.0 on end # Thermal Subsystem
place under thermal device
OK
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33131 )
Change subject: mb/google/sarien/variants/sarien: Set PCH Thermal Trip point to 77 degree C ......................................................................
Patch Set 5: Code-Review+1
Change looks good to me. I will let Duncan +2 this.
Hello Aaron Durbin, Duncan Laurie, build bot (Jenkins), Furquan Shaikh, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33131
to look at the new patch set (#6).
Change subject: mb/google/sarien/variants/sarien: Set PCH Thermal Trip point to 77 degree C ......................................................................
mb/google/sarien/variants/sarien: Set PCH Thermal Trip point to 77 degree C
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal Shutdown when S0ix is enabled.
BUG=None BRANCH=None TEST=Verified Thermal Device (B0: D20: F2) TSPM offset 0x1c [LTT (8:0)] value is 0xFE on Sarien.
Change-Id: Ibc336be0523ff4e65a818474907faf20fc417ff4 Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/sarien/variants/sarien/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/33131/6
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33131 )
Change subject: mb/google/sarien/variants/sarien: Set PCH Thermal Trip point to 77 degree C ......................................................................
Patch Set 6:
Patch Set 5: Code-Review+1
Change looks good to me. I will let Duncan +2 this.
I have uploaded new patch set 6 as per recent common/block/thermal patches merged based on pch thermal trip added under common_soc_config.
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33131 )
Change subject: mb/google/sarien/variants/sarien: Set PCH Thermal Trip point to 77 degree C ......................................................................
Patch Set 6:
Request to review this. Thanks.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33131 )
Change subject: mb/google/sarien/variants/sarien: Set PCH Thermal Trip point to 77 degree C ......................................................................
Patch Set 6: Code-Review+2
Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33131 )
Change subject: mb/google/sarien/variants/sarien: Set PCH Thermal Trip point to 77 degree C ......................................................................
mb/google/sarien/variants/sarien: Set PCH Thermal Trip point to 77 degree C
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal Shutdown when S0ix is enabled.
BUG=None BRANCH=None TEST=Verified Thermal Device (B0: D20: F2) TSPM offset 0x1c [LTT (8:0)] value is 0xFE on Sarien.
Change-Id: Ibc336be0523ff4e65a818474907faf20fc417ff4 Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/33131 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/google/sarien/variants/sarien/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 739a849..d3aab62 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -163,6 +163,9 @@
register "tcc_offset" = "10"
+ # PCH Thermal Trip Temperature in deg C + register "common_soc_config.pch_thermal_trip" = "77" + register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = {
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Furquan Shaikh (Code Review) -
Martin Roth (Code Review)
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Patrick Rudolph (Code Review)
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Sumeet R Pawnikar (Code Review)