Change in ...coreboot[master]: mainboard/google/kahlee: Configure debounce settings for interrupt GPIOs

[Daniel Kurtz (Code Review)]

Hello Daniel Kurtz,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/30999

to review the following change.

Change subject: mainboard/google/kahlee: Configure debounce settings for interrupt GPIOs
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mainboard/google/kahlee: Configure debounce settings for interrupt GPIOs

FT4 has a strange property where whenever the debounce registers for any
one gpio are changed, the FT4 disables interrupt propagation for ALL
gpio irqs for ~4ms.

In other words, if an edge interrupt of one gpio happens exactly during
this debounce-irq-off window immediately following the configuration of
another gpio, the interrupt will be lost.

It is quite difficult to deal with this in the kernel, since during kernel
boot time, drivers & devices are probed asynchronously, meaning it may
happen that an already loaded driver may miss an interrupt when some
later driver is being probed and configuring its gpio interrupt.

To eliminate this possibility, we pre-configure the debounce registers in
ram stage for all gpios that will be used as irqs later by the kernel
using the same configuration as used by the kernel, as per this table:

IRQ         Debounce
 Edge        Remove Glitch
 Level High  Preserve Low Glitch
 Level Low   Preserve High Glitch

Note that for GPIO9 we re-configure debounce in RAM section, since this
GPIO was originally configured without debounce in bootblock, which is
not changeable for devices with WP RO BIOS.  So the setting must also be
reconfigured in RAM to ensure it happens in RW BIOS.

Signed-off-by: Daniel Kurtz

BUG=b:113880780
BRANCH=none
TEST=Reboot stress test grunt (>100 times); no messages in dmesg like:
  tpm tpm0: Timeout waiting for TPM ready

Change-Id: Ic1bd269c196ca9b48157e177fd5834e2f5d5703a
---
M src/mainboard/google/kahlee/variants/baseboard/gpio.c
1 file changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/30999/1

diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
index e9ae28c..19dbc41 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c
+++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
@@ -35,6 +35,7 @@
    /* GPIO_9 - H1_PCH_INT_ODL, SCI */
    PAD_INT(GPIO_9, PULL_UP, EDGE_LOW, STATUS),
    PAD_SCI(GPIO_9, PULL_UP, EDGE_LOW),
+	PAD_DEBOUNCE(GPIO_9, REMOVE_GLITCH, DEBOUNCE_DISABLED),

/* GPIO_15 - EC_IN_RW_OD */
    PAD_GPI(GPIO_15, PULL_UP),
@@ -110,6 +111,7 @@

/* GPIO_5 - PCH_TRACKPAD_INT_3V3_ODL, SCI */
    PAD_SCI(GPIO_5, PULL_UP, EDGE_LOW),
+	PAD_DEBOUNCE(GPIO_5, PRESERVE_HIGH_GLITCH, DEBOUNCE_DISABLED),

/* GPIO_7 - APU_PWROK_OD (currently not used) */
    PAD_GPI(GPIO_7, PULL_UP),
@@ -117,11 +119,15 @@
    /* GPIO_8 - DDR_ALERT_3V3_L (currently not used) */
    PAD_GPI(GPIO_8, PULL_UP),

+	/* GPIO_9 - H1_PCH_INT_ODL, SCI */
+	PAD_DEBOUNCE(GPIO_9, REMOVE_GLITCH, DEBOUNCE_DISABLED),
+
    /* GPIO_10 - SLP_S0_L (currently not used) */
    PAD_NF(GPIO_10, S0A3_GPIO, PULL_UP),

/* GPIO_11 - TOUCHSCREEN_INT_3V3_ODL, SCI */
    PAD_SCI(GPIO_11, PULL_UP, EDGE_LOW),
+	PAD_DEBOUNCE(GPIO_11, REMOVE_GLITCH, DEBOUNCE_DISABLED),

/* GPIO_12 - EN_PP3300_TRACKPAD */
    PAD_GPO(GPIO_12, HIGH),
@@ -131,6 +137,7 @@

/* GPIO_14 - APU_HP_INT_ODL, SCI */
    PAD_SCI(GPIO_14, PULL_UP, EDGE_LOW),
+	PAD_DEBOUNCE(GPIO_14, REMOVE_GLITCH, DEBOUNCE_DISABLED),

/* GPIO_16 - USB_C0_OC_L */
    PAD_NF(GPIO_16, USB_OC0_L, PULL_UP),

[Martin Roth (Code Review)]

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30999 )

Change subject: mainboard/google/kahlee: Configure debounce settings for interrupt GPIOs
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Patch Set 1: Code-Review+2

(1 comment)

https://review.coreboot.org/#/c/30999/1/src/mainboard/google/kahlee/variants... 
File src/mainboard/google/kahlee/variants/baseboard/gpio.c:

https://review.coreboot.org/#/c/30999/1/src/mainboard/google/kahlee/variants... 
PS1, Line 122: /* GPIO_9 - H1_PCH_INT_ODL, SCI */
Might want a comment here that it's needed in reset for new systems and ram for existing systems.  Or not.  Up to you.

[Raul Rangel (Code Review)]

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30999 )

Change subject: mainboard/google/kahlee: Configure debounce settings for interrupt GPIOs
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Patch Set 1: Code-Review-1

Let's wait to submit this until we try keeping MASK_STS disabled.

[Daniel Kurtz (Code Review)]

Daniel Kurtz has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30999 )

Change subject: mainboard/google/kahlee: Configure debounce settings for interrupt GPIOs
......................................................................

Patch Set 1:
> Patch Set 1: Code-Review-1
>
> Let's wait to submit this until we try keeping MASK_STS disabled.

Ack.

[Daniel Kurtz (Code Review)]

Daniel Kurtz has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30999 )

Change subject: mainboard/google/kahlee: Configure debounce settings for interrupt GPIOs
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Abandoned

obsolete by CL:31082