Change in coreboot[master]: soc/amd/cezanne: add XHCI SCI/GEVENT setup

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51415 )

Change subject: soc/amd/cezanne: add XHCI SCI/GEVENT setup
......................................................................

soc/amd/cezanne: add XHCI SCI/GEVENT setup

Signed-off-by: Felix Held 
Change-Id: I32fd9b7165306266613e8497b5d07473b5fea02d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51415
Tested-by: build bot (Jenkins) 
Reviewed-by: Marshall Dawson 
---
M src/soc/amd/cezanne/Makefile.inc
A src/soc/amd/cezanne/xhci.c
2 files changed, 53 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Marshall Dawson: Looks good to me, approved

diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index aa82c99..f099ad8 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -35,6 +35,7 @@
 ramstage-y	+= reset.c
 ramstage-y	+= root_complex.c
 ramstage-y	+= uart.c
+ramstage-y	+= xhci.c

smm-y		+= gpio.c
 smm-y		+= smihandler.c
diff --git a/src/soc/amd/cezanne/xhci.c b/src/soc/amd/cezanne/xhci.c
new file mode 100644
index 0000000..a77830c
--- /dev/null
+++ b/src/soc/amd/cezanne/xhci.c
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/gpio_banks.h>
+#include <amdblocks/smi.h>
+#include <bootstate.h>
+#include <device/device.h>
+#include <drivers/usb/pci_xhci/pci_xhci.h>
+#include <soc/pci_devs.h>
+#include <soc/smi.h>
+
+static const struct sci_source xhci_sci_sources[] = {
+	{
+		.scimap = SMITYPE_XHC0_PME,
+		.gpe = GEVENT_31,
+		.direction = SMI_SCI_LVL_HIGH,
+		.level = SMI_SCI_EDG
+	},
+	{
+		.scimap = SMITYPE_XHC1_PME,
+		.gpe = GEVENT_31,
+		.direction = SMI_SCI_LVL_HIGH,
+		.level = SMI_SCI_EDG
+	}
+};
+
+enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe)
+{
+	if (dev->bus->dev->path.type != DEVICE_PATH_PCI)
+		return CB_ERR_ARG;
+
+	if (dev->bus->dev->path.pci.devfn != PCIE_ABC_A_DEVFN)
+		return CB_ERR_ARG;
+
+	if (dev->path.type != DEVICE_PATH_PCI)
+		return CB_ERR_ARG;
+
+	if (dev->path.pci.devfn == XHCI0_DEVFN)
+		*gpe = xhci_sci_sources[0].gpe;
+	else if (dev->path.pci.devfn == XHCI1_DEVFN)
+		*gpe = xhci_sci_sources[1].gpe;
+	else
+		return CB_ERR_ARG;
+
+	return CB_SUCCESS;
+}
+
+static void configure_xhci_sci(void *unused)
+{
+	gpe_configure_sci(xhci_sci_sources, ARRAY_SIZE(xhci_sci_sources));
+}
+
+BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, configure_xhci_sci, NULL);