[XS] Change in coreboot[main]: soc/mediatek/common/dp: Use DP_WRITE2BYTE if possible

[Yidi Lin (Code Review)]

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85918?usp=email )

(

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: soc/mediatek/common/dp: Use DP_WRITE2BYTE if possible
......................................................................

soc/mediatek/common/dp: Use DP_WRITE2BYTE if possible

This patch prevents wrong mask passing to mtk_dp_mask.

TEST=emerge-rauru coreboot, check FW screen

Change-Id: If8c801173089761db55992279045d053c60dcd86
Signed-off-by: Yidi Lin 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85918
Reviewed-by: Yu-Ping Wu 
Tested-by: build bot (Jenkins) 
---
M src/soc/mediatek/common/dp/dptx_hal.c
M src/soc/mediatek/common/dp/dptx_hal_common.c
2 files changed, 3 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Yu-Ping Wu: Looks good to me, approved

diff --git a/src/soc/mediatek/common/dp/dptx_hal.c b/src/soc/mediatek/common/dp/dptx_hal.c
index 70d69cb..28a1480 100644
--- a/src/soc/mediatek/common/dp/dptx_hal.c
+++ b/src/soc/mediatek/common/dp/dptx_hal.c
@@ -65,7 +65,7 @@
    mtk_dp_write_byte(mtk_dp, REG_303C_DP_ENCODER0_P0 + 1,
    		  BIT(7), BIT(7));
    DP_WRITE2BYTE(mtk_dp, REG_3040_DP_ENCODER0_P0, 0x2020);
-	mtk_dp_mask(mtk_dp, REG_3364_DP_ENCODER1_P0, 0x2020, 0xfff);
+	DP_WRITE2BYTE(mtk_dp, REG_3364_DP_ENCODER1_P0, 0x2020);
    mtk_dp_write_byte(mtk_dp, REG_3300_DP_ENCODER1_P0 + 1,
    		  0x2, BIT(1) | BIT(0));
    mtk_dp_write_byte(mtk_dp, REG_3364_DP_ENCODER1_P0 + 1,
diff --git a/src/soc/mediatek/common/dp/dptx_hal_common.c b/src/soc/mediatek/common/dp/dptx_hal_common.c
index 4ef07ac..3ba95d1 100644
--- a/src/soc/mediatek/common/dp/dptx_hal_common.c
+++ b/src/soc/mediatek/common/dp/dptx_hal_common.c
@@ -292,12 +292,12 @@

void dptx_hal_setsdp_downcnt_init_inhblanking(struct mtk_dp *mtk_dp, u16 value)
 {
-	mtk_dp_mask(mtk_dp, REG_3364_DP_ENCODER1_P0, value, 0xfff);
+	DP_WRITE2BYTE(mtk_dp, REG_3364_DP_ENCODER1_P0, value);
 }

void dptx_hal_setsdp_downcnt_init(struct mtk_dp *mtk_dp, u16 value)
 {
-	mtk_dp_mask(mtk_dp, REG_3040_DP_ENCODER0_P0, value, 0xfff);
+	DP_WRITE2BYTE(mtk_dp, REG_3040_DP_ENCODER0_P0, value);
 }

bool dptx_hal_auxread_bytes(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, size_t length,