Change in coreboot[master]: soc/amd/cezanne: enlarge clk_req bitfield

[Kevin Chiu (Code Review)]

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58029 )

Change subject: soc/amd/cezanne: enlarge clk_req bitfield
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soc/amd/cezanne: enlarge clk_req bitfield

Fix build overflow error if clk_req sets to CLK_ENABLE (0xff)

BUG=None
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage

Signed-off-by: Kevin Chiu 
Change-Id: I6bf59d7a3fefd94b09e5478bf98b0814414e2ef6
---
M src/vendorcode/amd/fsp/cezanne/platform_descriptors.h
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/58029/1

diff --git a/src/vendorcode/amd/fsp/cezanne/platform_descriptors.h b/src/vendorcode/amd/fsp/cezanne/platform_descriptors.h
index ada9bbd..24f0b87 100644
--- a/src/vendorcode/amd/fsp/cezanne/platform_descriptors.h
+++ b/src/vendorcode/amd/fsp/cezanne/platform_descriptors.h
@@ -199,7 +199,7 @@
    uint32_t	link_aspm		:2;	// See dxio_aspm_type
    uint32_t	link_aspm_L1_1		:1;	// En/Dis root port capabilities for L1.1
    uint32_t	link_aspm_L1_2		:1;	// En/Dis root port capabilities for L1.2
-	uint32_t	clk_req			:4;	// See cpm_clk_req
+	uint32_t	clk_req			:8;	// See cpm_clk_req
    uint8_t		link_hotplug;			// Currently unused by FSP
    uint8_t		slot_power_limit;		// Currently unused by FSP
    uint32_t	slot_power_limit_scale	:2;	// Currently unused by FSP