[M] Change in coreboot[main]: mb/google/nissa/var/telith: Reduce power limits

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85894?usp=email )

Change subject: mb/google/nissa/var/telith: Reduce power limits
......................................................................

mb/google/nissa/var/telith: Reduce power limits

When battery is not present, reduce power limits,
avoid inability to enter the system.

This will check the current battery status and configure cpu power
limits using current PD power value.

BUG=b:384883899
BRANCH=none
TEST=built and verified PL4 values,power engineer verify pass.

Change-Id: I7e0c7289c20c4ce51eae2a48eb8f09acfcb9e958
Signed-off-by: Kun Liu 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85894
Reviewed-by: Subrata Banik 
Reviewed-by: Eric Lai 
Reviewed-by: Kapil Porwal 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/brya/variants/baseboard/nissa/ramstage.c
M src/mainboard/google/brya/variants/telith/Makefile.mk
A src/mainboard/google/brya/variants/telith/ramstage.c
3 files changed, 93 insertions(+), 0 deletions(-)

Approvals:
  Eric Lai: Looks good to me, approved
  Subrata Banik: Looks good to me, approved
  Kapil Porwal: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/ramstage.c b/src/mainboard/google/brya/variants/baseboard/nissa/ramstage.c
index 64e1b14..a45b1eb 100644
--- a/src/mainboard/google/brya/variants/baseboard/nissa/ramstage.c
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/ramstage.c
@@ -2,8 +2,41 @@

#include <baseboard/gpio.h>
 #include <baseboard/variants.h>
+#include <device/pci_ops.h>
 #include <gpio.h>
+#include <soc/gpio.h>
 #include <soc/ramstage.h>
+#include <soc/pci_devs.h>
+#include <static.h>
+#include <intelblocks/power_limit.h>
+
+struct soc_power_limits_config *variant_get_soc_power_limit_config(void)
+{
+	config_t *config = config_of_soc();
+	size_t i;
+	struct device *sa = pcidev_path_on_root(SA_DEVFN_ROOT);
+	uint16_t sa_pci_id;
+	u8 tdp;
+
+	if (!sa)
+		return NULL;
+
+	sa_pci_id = pci_read_config16(sa, PCI_DEVICE_ID);
+
+	if (sa_pci_id == 0xffff)
+		return NULL;
+
+	tdp = get_cpu_tdp();
+
+	for (i = 0; i < ARRAY_SIZE(cpuid_to_adl); i++) {
+		if (sa_pci_id == cpuid_to_adl[i].cpu_id &&
+				tdp == cpuid_to_adl[i].cpu_tdp) {
+			return &config->power_limits_config[cpuid_to_adl[i].limits];
+		}
+	}
+
+	return NULL;
+}

void variant_configure_pads(void)
 {
diff --git a/src/mainboard/google/brya/variants/telith/Makefile.mk b/src/mainboard/google/brya/variants/telith/Makefile.mk
index f41cdfd..e7ef021 100644
--- a/src/mainboard/google/brya/variants/telith/Makefile.mk
+++ b/src/mainboard/google/brya/variants/telith/Makefile.mk
@@ -4,5 +4,6 @@
 romstage-y += gpio.c

ramstage-y += gpio.c
+ramstage-y += ramstage.c

ramstage-y += variant.c
diff --git a/src/mainboard/google/brya/variants/telith/ramstage.c b/src/mainboard/google/brya/variants/telith/ramstage.c
new file mode 100644
index 0000000..9156385
--- /dev/null
+++ b/src/mainboard/google/brya/variants/telith/ramstage.c
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <chip.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <ec/google/chromeec/ec.h>
+#include <intelblocks/power_limit.h>
+
+#define NO_BATTERY_PL4_WATTS_LIMIT	45
+
+static bool get_pd_power_watts(u32 *watts)
+{
+	int rv;
+	enum usb_chg_type type = USB_CHG_TYPE_UNKNOWN;
+	u16 volts_mv, current_ma;
+
+	rv = google_chromeec_get_usb_pd_power_info(&type, &current_ma, &volts_mv);
+	if (rv == 0 && type == USB_CHG_TYPE_PD) {
+		/* Detected USB-PD. Base on max value of adapter */
+		*watts = ((u32)current_ma * volts_mv) / 1000000;
+		return true;
+	}
+
+	printk(BIOS_WARNING, "Cannot get PD power info. rv = %d, usb_chg_type: %d\n", rv, type);
+	return false;
+}
+
+void variant_devtree_update(void)
+{
+	struct soc_power_limits_config *soc_config;
+	u32 watts;
+	u32 pl4_watts = NO_BATTERY_PL4_WATTS_LIMIT;
+
+	soc_config = variant_get_soc_power_limit_config();
+	if (soc_config == NULL)
+		return;
+
+	/*
+	 * If battery is not present or battery level is at or below critical threshold
+	 * to boot a platform with the power efficient configuration, limit PL4
+	 * settings.
+	 */
+	if (!google_chromeec_is_battery_present()) {
+		/* Adjust PL4 values according to current PD power */
+		if (get_pd_power_watts(&watts)) {
+			if (watts < NO_BATTERY_PL4_WATTS_LIMIT)
+				pl4_watts = watts - 5;
+			else
+				pl4_watts = 40;
+		}
+		if (soc_config->tdp_pl4 > pl4_watts) {
+			printk(BIOS_INFO, "override PL4 settings to %d watts\n", pl4_watts);
+			soc_config->tdp_pl4 = pl4_watts;
+		}
+	}
+}