Change in coreboot[master]: intel/soc: skl,apl,cnl,icl,tgl: add INTRUDER relevant registers
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39263 )
Change subject: intel/soc: skl,apl,cnl,icl,tgl: add INTRUDER relevant registers ......................................................................
intel/soc: skl,apl,cnl,icl,tgl: add INTRUDER relevant registers
Add registers that are relevant for the case intrusion detection functionality.
Intel documents: 332691-003EN, 335193-006, 341081-001, ...
Change-Id: If12d21e8e6721abb877cbbfbbba8f0127a86d96b Signed-off-by: Michael Niewöhner foss@mniewoehner.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/39263 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Aaron Durbin adurbin@chromium.org Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net --- M src/soc/intel/apollolake/include/soc/smbus.h M src/soc/intel/cannonlake/include/soc/smbus.h M src/soc/intel/icelake/include/soc/smbus.h M src/soc/intel/skylake/include/soc/smbus.h M src/soc/intel/tigerlake/include/soc/smbus.h 5 files changed, 26 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Aaron Durbin: Looks good to me, approved
diff --git a/src/soc/intel/apollolake/include/soc/smbus.h b/src/soc/intel/apollolake/include/soc/smbus.h index 4b252d6..965e8bc 100644 --- a/src/soc/intel/apollolake/include/soc/smbus.h +++ b/src/soc/intel/apollolake/include/soc/smbus.h @@ -21,8 +21,13 @@ #define TCO_TIMEOUT (1 << 3) #define TCO2_STS 0x06 #define TCO_STS_SECOND_TO (1 << 1) +#define TCO_INTRD_DET (1 << 0) #define TCO1_CNT 0x08 #define TCO_LOCK (1 << 12) #define TCO_TMR_HLT (1 << 11) +#define TCO2_CNT 0x0A +#define TCO_INTRD_SEL_MASK (3 << 1) +#define TCO_INTRD_SEL_SMI (1 << 2) +#define TCO_INTRD_SEL_INT (1 << 1)
#endif diff --git a/src/soc/intel/cannonlake/include/soc/smbus.h b/src/soc/intel/cannonlake/include/soc/smbus.h index 54d0d6c..60d1557 100644 --- a/src/soc/intel/cannonlake/include/soc/smbus.h +++ b/src/soc/intel/cannonlake/include/soc/smbus.h @@ -24,9 +24,14 @@ #define TCO_TIMEOUT (1 << 3) #define TCO2_STS 0x06 #define TCO_STS_SECOND_TO (1 << 1) +#define TCO_INTRD_DET (1 << 0) #define TCO1_CNT 0x08 #define TCO_LOCK (1 << 12) #define TCO_TMR_HLT (1 << 11) +#define TCO2_CNT 0x0A +#define TCO_INTRD_SEL_MASK (3 << 1) +#define TCO_INTRD_SEL_SMI (1 << 2) +#define TCO_INTRD_SEL_INT (1 << 1)
/* * Default slave address value for PCH. This value is set to match default diff --git a/src/soc/intel/icelake/include/soc/smbus.h b/src/soc/intel/icelake/include/soc/smbus.h index 9d8fe46..2277ca9 100644 --- a/src/soc/intel/icelake/include/soc/smbus.h +++ b/src/soc/intel/icelake/include/soc/smbus.h @@ -21,9 +21,14 @@ #define TCO_TIMEOUT (1 << 3) #define TCO2_STS 0x06 #define TCO_STS_SECOND_TO (1 << 1) +#define TCO_INTRD_DET (1 << 0) #define TCO1_CNT 0x08 #define TCO_LOCK (1 << 12) #define TCO_TMR_HLT (1 << 11) +#define TCO2_CNT 0x0A +#define TCO_INTRD_SEL_MASK (3 << 1) +#define TCO_INTRD_SEL_SMI (1 << 2) +#define TCO_INTRD_SEL_INT (1 << 1)
/* * Default slave address value for PCH. This value is set to match default diff --git a/src/soc/intel/skylake/include/soc/smbus.h b/src/soc/intel/skylake/include/soc/smbus.h index ee257ea..216e864 100644 --- a/src/soc/intel/skylake/include/soc/smbus.h +++ b/src/soc/intel/skylake/include/soc/smbus.h @@ -23,10 +23,15 @@ #define TCO1_STS 0x04 #define TCO_TIMEOUT (1 << 3) #define TCO2_STS 0x06 -#define TCO_STS_SECOND_TO 0x02 +#define TCO_STS_SECOND_TO (1 << 1) +#define TCO_INTRD_DET (1 << 0) #define TCO1_CNT 0x08 #define TCO_LOCK (1 << 12) #define TCO_TMR_HLT (1 << 11) +#define TCO2_CNT 0x0A +#define TCO_INTRD_SEL_MASK (3 << 1) +#define TCO_INTRD_SEL_SMI (1 << 2) +#define TCO_INTRD_SEL_INT (1 << 1)
/* SMBus I/O bits. */ #define SMBUS_SLAVE_ADDR 0x24 diff --git a/src/soc/intel/tigerlake/include/soc/smbus.h b/src/soc/intel/tigerlake/include/soc/smbus.h index 50ea044..0ad565a 100644 --- a/src/soc/intel/tigerlake/include/soc/smbus.h +++ b/src/soc/intel/tigerlake/include/soc/smbus.h @@ -29,9 +29,14 @@ #define TCO_TIMEOUT (1 << 3) #define TCO2_STS 0x06 #define TCO_STS_SECOND_TO (1 << 1) +#define TCO_INTRD_DET (1 << 0) #define TCO1_CNT 0x08 #define TCO_LOCK (1 << 12) #define TCO_TMR_HLT (1 << 11) +#define TCO2_CNT 0x0A +#define TCO_INTRD_SEL_MASK (3 << 1) +#define TCO_INTRD_SEL_SMI (1 << 2) +#define TCO_INTRD_SEL_INT (1 << 1)
/* * Default slave address value for PCH. This value is set to match default
-
Patrick Georgi (Code Review)