[S] Change in coreboot[master]: soc/amd/cezanne/acpi: use ROOT_BRIDGE macro

[Felix Held (Code Review)]

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel.

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75592?usp=email )

Change subject: soc/amd/cezanne/acpi: use ROOT_BRIDGE macro
......................................................................

soc/amd/cezanne/acpi: use ROOT_BRIDGE macro

Use the ROOT_BRIDGE macro in soc.asl to replace the pci0.asl file. The
soc/amd/common/acpi/lpc.asl file which was included in the now removed
pci0.asl file now gets included in the correct scope in the soc.asl
file.

Signed-off-by: Felix Held 
Change-Id: Ia8f0f1619a71f4ab2051714a9d8c7eb200845390
---
D src/soc/amd/cezanne/acpi/pci0.asl
M src/soc/amd/cezanne/acpi/soc.asl
2 files changed, 7 insertions(+), 25 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/75592/1

diff --git a/src/soc/amd/cezanne/acpi/pci0.asl b/src/soc/amd/cezanne/acpi/pci0.asl
deleted file mode 100644
index c778578..0000000
--- a/src/soc/amd/cezanne/acpi/pci0.asl
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Device(PCI0) {
-	Name(_HID, EISAID("PNP0A08"))	/* PCI Express Root Bridge */
-	Name(_CID, EISAID("PNP0A03"))	/* PCI Root Bridge */
-
-	/* Operating System Capabilities Method */
-	Method(_OSC, 4) {
-		CreateDWordField(Arg3, 0, CDW1) /* Capabilities dword 1 */
-
-		/* Check for proper PCI/PCIe UUID */
-		If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) {
-			/* Let OS control everything */
-			Return (Arg3)
-		} Else {
-			CDW1 |= 4	/* Unrecognized UUID */
-			Return (Arg3)
-		}
-	}
-
-	/* 0:14.3 - LPC */
-	#include <soc/amd/common/acpi/lpc.asl>
-
-} /* End PCI0 scope */
diff --git a/src/soc/amd/cezanne/acpi/soc.asl b/src/soc/amd/cezanne/acpi/soc.asl
index f8f7a8a..5d0d50f 100644
--- a/src/soc/amd/cezanne/acpi/soc.asl
+++ b/src/soc/amd/cezanne/acpi/soc.asl
@@ -16,7 +16,13 @@

#include "mmio.asl"

-	#include "pci0.asl"
+	#include <soc/amd/common/acpi/pci_root.asl>
+
+	ROOT_BRIDGE(PCI0)
+
+	Scope(PCI0) {
+		#include <soc/amd/common/acpi/lpc.asl>
+	} /* End PCI0 scope */
 } /* End _SB scope */

#include <soc/amd/common/acpi/alib.asl>