Change in coreboot[master]: nb/intel/haswell: Use `chromeos_reserve_ram_oops` function

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46980 )

Change subject: nb/intel/haswell: Use `chromeos_reserve_ram_oops` function
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nb/intel/haswell: Use `chromeos_reserve_ram_oops` function

Taken from Broadwell and assumed to be equivalent.

Change-Id: Iffc2e3450e98182139dc5020b466186d0d28d20c
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/haswell/northbridge.c
1 file changed, 4 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/46980/1

diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index 2d19ccd..a6f187c 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -13,6 +13,7 @@
 #include <device/pci_ops.h>
 #include <boot/tables.h>
 #include <security/intel/txt/txt_register.h>
+#include <vendorcode/google/chromeos/chromeos.h>

#include "chip.h"
 #include "haswell.h"
@@ -373,11 +374,9 @@
    mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
    reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10);

-#if CONFIG(CHROMEOS_RAMOOPS)
-	reserved_ram_resource(dev, index++,
-			CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
-			CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE  >> 10);
-#endif
+	if (CONFIG(CHROMEOS))
+		chromeos_reserve_ram_oops(dev, index++);
+
    *resource_cnt = index;
 }

[Angel Pons (Code Review)]

Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/46980 )

Change subject: nb/intel/haswell: Use `chromeos_reserve_ram_oops` function
......................................................................

Abandoned

Superseded