Change in coreboot[master]: nb/intel/gm45/raminit: Use CxDRT*_MCHBAR instead of magic numbers

[Jonathan Neuschäfer (Code Review)]

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/23709

Change subject: nb/intel/gm45/raminit: Use CxDRT*_MCHBAR instead of magic numbers
......................................................................

nb/intel/gm45/raminit: Use CxDRT*_MCHBAR instead of magic numbers

This is hopefully more readable.

TEST=Build lenovo/x200 with and without this patch, compare
build/cbfs/fallback/romstage.elf, notice no substantial differences.

Change-Id: I079d5353633a3d58ce0e5e616f3fad687a064d65
Signed-off-by: Jonathan Neuschäfer 
---
M src/northbridge/intel/gm45/raminit.c
1 file changed, 6 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/23709/1

diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index a44e397..d4e60b7 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -1798,10 +1798,12 @@
    /* Perform receive-enable calibration. */
    raminit_receive_enable_calibration(timings, dimms);
    /* Lend clock values from receive-enable calibration. */
-	MCHBAR32(0x1224) = (MCHBAR32(0x1224) & ~(0xf0)) |
-			   ((((MCHBAR32(0x121c) >> 7) - 1) & 0xf) << 4);
-	MCHBAR32(0x1324) = (MCHBAR32(0x1324) & ~(0xf0)) |
-			   ((((MCHBAR32(0x131c) >> 7) - 1) & 0xf) << 4);
+	MCHBAR32(CxDRT5_MCHBAR(0)) =
+		(MCHBAR32(CxDRT5_MCHBAR(0)) & ~(0xf0)) |
+		((((MCHBAR32(CxDRT3_MCHBAR(0)) >> 7) - 1) & 0xf) << 4);
+	MCHBAR32(CxDRT5_MCHBAR(1)) =
+		(MCHBAR32(CxDRT5_MCHBAR(1)) & ~(0xf0)) |
+		((((MCHBAR32(CxDRT3_MCHBAR(1)) >> 7) - 1) & 0xf) << 4);

/* Perform read/write training for high clock rate. */
    if (timings->mem_clock == MEM_CLOCK_1067MT) {