[S] Change in coreboot[main]: soc/intel/alderlake: Add IRQ mapping for PEG PCI-E ports

[Sean Rhodes (Code Review)]

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Michał Żygowski, Nick Vaccaro, Subrata Banik.

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84620?usp=email )

Change subject: soc/intel/alderlake: Add IRQ mapping for PEG PCI-E ports
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Patch Set 6:

(1 comment)

Patchset:

PS4:
> Could you please share the warning message? and also the output of  […]

Error:
`[    0.852250] pcieport 0000:00:06.0: can't derive routing for PCI INT A`
Without patch:
```
 122:          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0  IR-PCI-MSI-0000:00:06.0    0-edge      PCIe PME, aerdrv

00:06.0 PCI bridge: Intel Corporation Raptor Lake PCIe 4.0 Graphics Port (prog-if 00 [Normal decode])
    Interrupt: pin D routed to IRQ 122
```
With patch:
```
 122:          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0          0  IR-PCI-MSI-0000:00:06.0    0-edge      PCIe PME, aerdrv

00:06.0 PCI bridge: Intel Corporation Raptor Lake PCIe 4.0 Graphics Port (prog-if 00 [Normal decode])
    Interrupt: pin D routed to IRQ 122
```