Change in coreboot[master]: soc/intel/jasperlake: Send End-of-Post message to CSE

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Patrick Rudolph.
Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55633 )

Change subject: soc/intel/jasperlake: Send End-of-Post message to CSE
......................................................................

soc/intel/jasperlake: Send End-of-Post message to CSE

This is done to ensure the CSE will not execute any pre-boot commands
after it receives this command.

Signed-off-by: Tim Wawrzynczak 
Change-Id: I36fe448ff279ba054ad5e79e71c995dc915db21e
---
M src/soc/intel/jasperlake/Kconfig
M src/soc/intel/jasperlake/fsp_params.c
2 files changed, 3 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/55633/1

diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index f019026..af15a74 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -59,6 +59,7 @@
    select SOC_INTEL_COMMON_FSP_RESET
    select SOC_INTEL_COMMON_PCH_BASE
    select SOC_INTEL_COMMON_RESET
+	select SOC_INTEL_CSE_SET_EOP
    select SSE2
    select SUPPORT_CPU_UCODE_IN_CBFS
    select TSC_MONOTONIC_TIMER
diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c
index 4f2b936..c1aa4dd 100644
--- a/src/soc/intel/jasperlake/fsp_params.c
+++ b/src/soc/intel/jasperlake/fsp_params.c
@@ -99,8 +99,8 @@
    	params->RtcMemoryLock = 1;
    }

-	/* Enable End of Post in PEI phase */
-	params->EndOfPostMessage = EOP_PEI;
+	/* Disable FSP sending EOP, coreboot sends it instead. */
+	params->EndOfPostMessage = EOP_DISABLE;

/* Legacy 8254 timer support */
    params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER);