Change in coreboot[master]: soc/intel/alderlake: add processor power limits control support

[Sumeet R Pawnikar (Code Review)]

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph.
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51397 )

Change subject: soc/intel/alderlake: add processor power limits control support
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Patch Set 1:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/51397/comment/7c8781e7_ed4659c4 
PS1, Line 14: test
> What was tested?

Verified these PL1 and PL2 values using corbeoot logs.

File src/soc/intel/alderlake/systemagent.c:

https://review.coreboot.org/c/coreboot/+/51397/comment/081f246b_3e2eaa70 
PS1, Line 63: Configure turbo power limits 1ms after reset complete bit
> Is this captured in the BWG?

This delay time is coming as legacy on IA. It's captured in document 619503 mentioned in this file header under package power register.