Dave Frodin (dave.frodin@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5968
-gerrit
commit 1bb4c55c90c4911fd8cd36df7e6d0a3c4aa91a8c Author: Bruce Griffith Bruce.Griffith@se-eng.com Date: Tue Jun 10 05:10:19 2014 -0600
AMD Lamar: Add a new AMD FP3 socket mainboard
Add a new mainboard based on AMD's Family 15 Model 30 processor. The board will boot DOS, Ubuntu 14.10 and Windows 7.
Change-Id: I2f73c396247239d54f978846e8958950697d7464 Signed-off-by: Bruce Griffith Bruce.Griffith@se-eng.com Signed-off-by: Dave Frodin dave.frodin@se-eng.com --- src/mainboard/amd/Kconfig | 3 + src/mainboard/amd/lamar/BiosCallOuts.c | 353 +++++++++++++++ src/mainboard/amd/lamar/Kconfig | 102 +++++ src/mainboard/amd/lamar/Makefile.inc | 26 ++ src/mainboard/amd/lamar/PlatformGnbPcie.c | 138 ++++++ src/mainboard/amd/lamar/acpi/AmdImc.asl | 115 +++++ src/mainboard/amd/lamar/acpi/gpe.asl | 77 ++++ src/mainboard/amd/lamar/acpi/mainboard.asl | 43 ++ src/mainboard/amd/lamar/acpi/routing.asl | 231 ++++++++++ src/mainboard/amd/lamar/acpi/sata.asl | 1 + src/mainboard/amd/lamar/acpi/si.asl | 28 ++ src/mainboard/amd/lamar/acpi/sleep.asl | 103 +++++ src/mainboard/amd/lamar/acpi/superio.asl | 1 + src/mainboard/amd/lamar/acpi/thermal.asl | 1 + src/mainboard/amd/lamar/acpi/usb_oc.asl | 31 ++ src/mainboard/amd/lamar/acpi_tables.c | 59 +++ src/mainboard/amd/lamar/agesawrapper.c | 661 +++++++++++++++++++++++++++++ src/mainboard/amd/lamar/board_info.txt | 5 + src/mainboard/amd/lamar/cmos.layout | 114 +++++ src/mainboard/amd/lamar/devicetree.cb | 118 +++++ src/mainboard/amd/lamar/dsdt.asl | 91 ++++ src/mainboard/amd/lamar/get_bus_conf.c | 150 +++++++ src/mainboard/amd/lamar/irq_tables.c | 112 +++++ src/mainboard/amd/lamar/mainboard.c | 208 +++++++++ src/mainboard/amd/lamar/mptable.c | 170 ++++++++ src/mainboard/amd/lamar/romstage.c | 138 ++++++ 26 files changed, 3079 insertions(+)
diff --git a/src/mainboard/amd/Kconfig b/src/mainboard/amd/Kconfig index cc5679a..8ae8be7 100644 --- a/src/mainboard/amd/Kconfig +++ b/src/mainboard/amd/Kconfig @@ -41,6 +41,8 @@ config BOARD_AMD_PARMER bool "Parmer" config BOARD_AMD_THATCHER bool "Thatcher" +config BOARD_AMD_LAMAR + bool "Lamar" config BOARD_AMD_OLIVEHILL bool "Olive Hill" config BOARD_AMD_OLIVEHILLPLUS @@ -66,6 +68,7 @@ source "src/mainboard/amd/torpedo/Kconfig" source "src/mainboard/amd/union_station/Kconfig" source "src/mainboard/amd/parmer/Kconfig" source "src/mainboard/amd/thatcher/Kconfig" +source "src/mainboard/amd/lamar/Kconfig" source "src/mainboard/amd/olivehill/Kconfig" source "src/mainboard/amd/olivehillplus/Kconfig"
diff --git a/src/mainboard/amd/lamar/BiosCallOuts.c b/src/mainboard/amd/lamar/BiosCallOuts.c new file mode 100644 index 0000000..f9d76ee --- /dev/null +++ b/src/mainboard/amd/lamar/BiosCallOuts.c @@ -0,0 +1,353 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "AGESA.h" +#include "amdlib.h" +#include <northbridge/amd/pi/BiosCallOuts.h> +#include "Ids.h" +#include "OptionsIds.h" +#include "heapManager.h" +#include "FchPlatform.h" +#include "cbfs.h" +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) +#include "imc.h" +#endif +#include "hudson.h" +#include <stdlib.h> +#include <device/azalia.h> + +static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); + +const BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, + {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, + {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, + {AGESA_READ_SPD, agesa_ReadSpd }, + {AGESA_DO_RESET, agesa_Reset }, + {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, + {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, + {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, + {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, + {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, + {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } +}; +const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); + +/** + * Realtek ALC272 CODEC Verb Table + */ +static const CODEC_ENTRY Alc272_VerbTbl[] = { + { 0x11, 0x411111F0 }, /* - S/PDIF Output 2 */ + { 0x12, 0x411111F0 }, /* - Digital Mic 1/2 [GPIO0] */ + { 0x13, 0x411111F0 }, /* - Digital Mic 3/4 [GPIO1] */ + { 0x14, 0x411111F0 }, /* Port D - Front Panel headphone */ + { 0x15, 0x411111F0 }, /* Port A - Surround */ + { 0x17, 0x411111F0 }, /* Port H - Mono */ + { 0x18, /* Port B - MIC - pink jack */ + (AZALIA_PINCFG_PORT_JACK << 30) + | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24) + | (AZALIA_PINCFG_DEVICE_MICROPHONE << 20) + | (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16) + | (AZALIA_PINCFG_COLOR_PINK << 12) + | (4 << 4) + | (0 << 0) + }, + { 0x19, 0x411111F0 }, /* Port F - Front Panel Mic */ + { 0x1A, /* Port C - LineIn1 - blue jack */ + (AZALIA_PINCFG_PORT_JACK << 30) + | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24) + | (AZALIA_PINCFG_DEVICE_LINEIN << 20) + | (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16) + | (AZALIA_PINCFG_COLOR_BLUE << 12) + | (4 << 4) + | (0xF << 0) + }, + { 0x1B, 0x411111F0 }, /* Port E - Front Panel line-out */ + { 0x1D, 0x40251E05 }, /* PC Beep - (internal) */ + { 0x1E, /* S/PDIF - Internal Header */ + (AZALIA_PINCFG_PORT_JACK << 30) + | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_FRONT) << 24) + | (AZALIA_PINCFG_DEVICE_SPDIF_OUT << 20) + | (AZALIA_PINCFG_CONN_RCA << 16) + | (AZALIA_PINCFG_COLOR_BLACK << 12) + | (1 << 4) + | (0 << 0) + }, + { 0x21, /* Port I - HPout - green jack */ + (AZALIA_PINCFG_PORT_JACK << 30) + | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24) + | (AZALIA_PINCFG_DEVICE_HP_OUT << 20) + | (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16) + | (AZALIA_PINCFG_COLOR_GREEN << 12) + | (4 << 4) + | (0 << 0) + }, + { 0xFF, 0xFFFFFFFF }, +}; + +static const CODEC_TBL_LIST CodecTableList[] = +{ + {0x10ec0272, (CODEC_ENTRY*)&Alc272_VerbTbl[0]}, + {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} +}; + +#define FAN_INPUT_INTERNAL_DIODE 0 +#define FAN_INPUT_TEMP0 1 +#define FAN_INPUT_TEMP1 2 +#define FAN_INPUT_TEMP2 3 +#define FAN_INPUT_TEMP3 4 +#define FAN_INPUT_TEMP0_FILTER 5 +#define FAN_INPUT_ZERO 6 +#define FAN_INPUT_DISABLED 7 + +#define FAN_AUTOMODE (1 << 0) +#define FAN_LINEARMODE (1 << 1) +#define FAN_STEPMODE ~(1 << 1) +#define FAN_POLARITY_HIGH (1 << 2) +#define FAN_POLARITY_LOW ~(1 << 2) + +/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ +#define FREQ_28KHZ 0x0 +#define FREQ_25KHZ 0x1 +#define FREQ_23KHZ 0x2 +#define FREQ_21KHZ 0x3 +#define FREQ_29KHZ 0x4 +#define FREQ_18KHZ 0x5 +#define FREQ_100HZ 0xF7 +#define FREQ_87HZ 0xF8 +#define FREQ_58HZ 0xF9 +#define FREQ_44HZ 0xFA +#define FREQ_35HZ 0xFB +#define FREQ_29HZ 0xFC +#define FREQ_22HZ 0xFD +#define FREQ_14HZ 0xFE +#define FREQ_11HZ 0xFF + +/* + * Hardware Monitor Fan Control + * Hardware limitation: + * HWM will fail to read the input temperature via I2C if other + * software switches the I2C address. AMD recommends using IMC + * to control fans, instead of HWM. + */ +static void oem_fan_control(FCH_DATA_BLOCK *FchParams) +{ + FCH_HWM_FAN_CTR oem_factl[5] = { + /*temperature input, fan mode, frequency, low_duty, med_duty, multiplier, lowtemp, medtemp, hightemp, LinearRange, LinearHoldCount */ + /* FanOUT0 Fan header J32 */ + {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, + /* FanOUT1 Fan header J31*/ + {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, + {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, + {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, + {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, + }; + LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof (FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader); + + /* Enable IMC fan control. the recommended way */ +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) + + imc_reg_init(); + + /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ + FchParams->Hwm.HwMonitorEnable = TRUE; + FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 0 disable, 1 enable TSI Auto Polling */ + + FchParams->Imc.ImcEnable = TRUE; + FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ + FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */ + + LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); + + /* Thermal Zone Parameter */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e; //6 | BIT3; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x54; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x02; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM steping rate in unit of PWM level percentage */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00; + + /* IMC Fan Policy temperature thresholds */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46; /*AC0 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; + + /* IMC Fan Policy PWM Settings */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x5a; /* AL0 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x46; /* AL1 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0x28; /* AL2 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ + + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01; /* Zone */ + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg6 = 0x90; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg7 = 0; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */ + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg9 = 0; + + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg1 = 0x01; /* zone */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg2 = 60; /*AC0 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg3 = 40; /*AC1 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg4 = 0; /*AC2 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg5 = 0; /*AC3 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg6 = 0; /*AC4 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegA = 0; /*critical threshold* in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegB = 0x00; + + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg1 = 0x01; /*Zone */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg2 = 0; /* AL0 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg3 = 0; /* AL1 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg4 = 0; /* AL2 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg5 = 0x00; /* AL3 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg6 = 0x00; /* AL4 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg7 = 0x00; /* AL5 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg8 = 0x00; /* AL6 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg9 = 0x00; /* AL7 percentage */ + + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2; /* Zone */ + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg7 = 2; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg8 = 5; /* PWM steping rate in unit of PWM level percentage */ + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg9 = 0; + + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3; /* Zone */ + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg6 = 0x0; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg7 = 0; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */ + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0; + + /* IMC Function */ + FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333;//BIT0 | BIT4 |BIT8; + + /* NOTE: + * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, + * AGESA put EcDefaultMessage as global data in ROM, so we can't override it. + * so we remove it from AGESA code. Please See FchInitLateHwm. + */ + +#else /* HWM fan control, using the alternative method */ + FchParams->Imc.ImcEnable = FALSE; + FchParams->Hwm.HwMonitorEnable = TRUE; + FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ + +#endif /* CONFIG_HUDSON_IMC_FWM */ +} + +/** + * Fch Oem setting callback + * + * Configure platform specific Hudson device, + * such Azalia, SATA, IMC etc. + */ +static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) +{ + AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr; + if (StdHeader->Func == AMD_INIT_RESET) { + FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; + printk(BIOS_DEBUG, "\nFch OEM config in INIT RESET\n"); + //FchParams->EcChannel0 = TRUE; /* logical devicd 3 */ +#if CONFIG_HUDSON_LEGACY_FREE + FchParams->LegacyFree = 1; +#endif + + /* Turn on FCH GPP slots */ + FchParams->FchReset.GppEnable = TRUE; + FchParams->Gpp.GppFunctionEnable = TRUE; + FchParams->Gpp.GppLinkConfig = PortA1B1C1D1; + FchParams->Gpp.PortCfg[0].PortPresent = TRUE; + FchParams->Gpp.PortCfg[1].PortPresent = TRUE; + FchParams->Gpp.PortCfg[2].PortPresent = TRUE; + FchParams->Gpp.PortCfg[3].PortPresent = TRUE; + +#if CONFIG_HUDSON_SATA_IDE || CONFIG_HUDSON_SATA_AHCI + FchParams->FchReset.SataEnable = TRUE; +#else + FchParams->FchReset.SataEnable = FALSE; +#endif +#if CONFIG_HUDSON_SATA_IDE || CONFIG_HUDSON_SATA_LEGACY_IDE + FchParams->FchReset.IdeEnable = TRUE; +#else + FchParams->FchReset.IdeEnable = FALSE; +#endif + } else if (StdHeader->Func == AMD_INIT_ENV) { + FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData; + printk(BIOS_DEBUG, "Fch OEM config in INIT ENV"); + + /* Turn on FCH GPP slots */ + FchParams->Gpp.GppFunctionEnable = TRUE; + FchParams->Gpp.GppLinkConfig = PortA1B1C1D1; + + /* Azalia Controller OEM Codec Table Pointer */ + FchParams->Azalia.AzaliaPinCfg = TRUE; + FchParams->Azalia.AzaliaConfig = (const AZALIA_PIN){ + .AzaliaSdin0 = (CONFIG_AZ_PIN>>0) & 0x03, + .AzaliaSdin1 = (CONFIG_AZ_PIN>>2) & 0x03, + .AzaliaSdin2 = (CONFIG_AZ_PIN>>4) & 0x03, + .AzaliaSdin3 = (CONFIG_AZ_PIN>>6) & 0x03 + }; + FchParams->Azalia.AzaliaOemCodecTablePtr = CodecTableList; + /* Azalia Controller Front Panel OEM Table Pointer */ + + /* Fan Control */ + oem_fan_control(FchParams); + } + printk(BIOS_DEBUG, " Done\n"); + + return AGESA_SUCCESS; +} diff --git a/src/mainboard/amd/lamar/Kconfig b/src/mainboard/amd/lamar/Kconfig new file mode 100644 index 0000000..4226e62 --- /dev/null +++ b/src/mainboard/amd/lamar/Kconfig @@ -0,0 +1,102 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +if BOARD_AMD_LAMAR + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_AMD_PI_00630F01 + select NORTHBRIDGE_AMD_PI_00630F01 + select SOUTHBRIDGE_AMD_PI_BOLTON + select SUPERIO_FINTEK_F81216H + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE +# select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_8192 + select GFXUMA + +config MAINBOARD_DIR + string + default amd/lamar + +config MAINBOARD_PART_NUMBER + string + default "DB-FP3" + +config MAINBOARD_SERIAL_NUMBER + string + default "52198A" + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 4 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + +config IRQ_SLOT_COUNT + int + default 11 + +config RAMTOP + hex + default 0x1000000 + +config HEAP_SIZE + hex + default 0xc0000 + + +config RAMBASE + hex + default 0x200000 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config HUDSON_XHCI_FWM_FILE + string + default "3rdparty/southbridge/amd/bolton/xhci.bin" + +config AZ_PIN + hex + default 0x02 + +config ENABLE_DP3_DAUGHTER_CARD_IN_J120 + bool "Use J120 as an additional graphics port" + default n + help + The PCI Express slot at J120 can be configured as an additional + DisplayPort connector using an adapter card from AMD or as a normal + PCI Express (x4) slot. + + By default, the connector is configured as a PCI Express (x4) slot. + + Select this option to enable the slot for use with one of AMD's + passive graphics port expander cards (only available from AMD). + +endif # BOARD_AMD_LAMAR diff --git a/src/mainboard/amd/lamar/Makefile.inc b/src/mainboard/amd/lamar/Makefile.inc new file mode 100644 index 0000000..ec584cb --- /dev/null +++ b/src/mainboard/amd/lamar/Makefile.inc @@ -0,0 +1,26 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +romstage-y += agesawrapper.c +romstage-y += BiosCallOuts.c +romstage-y += PlatformGnbPcie.c + +ramstage-y += agesawrapper.c +ramstage-y += BiosCallOuts.c +ramstage-y += PlatformGnbPcie.c diff --git a/src/mainboard/amd/lamar/PlatformGnbPcie.c b/src/mainboard/amd/lamar/PlatformGnbPcie.c new file mode 100644 index 0000000..0d65ad5 --- /dev/null +++ b/src/mainboard/amd/lamar/PlatformGnbPcie.c @@ -0,0 +1,138 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * 2013 - 2014 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <northbridge/amd/pi/agesawrapper.h> + +#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE + +const PCIe_PORT_DESCRIPTOR PortList [] = { + + /* + * Lanes to pins to PCI device mapping can be found in section 2.12 of the + * BIOS and Kernel Developer's Guide for AMD Family 15h Models 30h-3Fh + */ + + { /* PCIe x16 Connector J119, DP4/5/6, GFX[15:0], Lanes [31:16], PCI 00:02.1 */ + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 31), + PCIE_PORT_DATA_INITIALIZER_V2 ( + PortEnabled, + ChannelTypeExt6db, 0, 0, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, + 175, + 0 + ) + }, + + { /* PCIe x4 Connector J118, GPP[3:0], Lanes [11:8], PCI 00:03.2 */ + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 11), + PCIE_PORT_DATA_INITIALIZER_V2 ( + PortEnabled, + ChannelTypeExt6db, 0, 0, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, + 176, + 0 + ) + }, + + { /* PCIe x4 Connector J120, GPP[7:4], Lanes [15:12] */ + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER ( + IS_ENABLED(CONFIG_ENABLE_DP3_DAUGHTER_CARD_IN_J120) ? PcieUnusedEngine : PciePortEngine, + 12, 15 + ), + PCIE_PORT_DATA_INITIALIZER_V2 ( + PortEnabled, + ChannelTypeExt6db, 0, 0, + HotplugDisabled, + PcieGenMaxSupported, PcieGenMaxSupported, + AspmDisabled, + 177, + 0 + ) + }, + +}; + +static const PCIe_DDI_DESCRIPTOR DdiList [] = { + { /* DP3 */ + 0, + PCIE_ENGINE_DATA_INITIALIZER ( + IS_ENABLED(CONFIG_ENABLE_DP3_DAUGHTER_CARD_IN_J120) ? PcieDdiEngine : PcieUnusedEngine, + 12, 15 + ), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux4, Hdp4) + }, + + { /* DP2 */ + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 36, 39), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux3, Hdp3) + }, + + { /* DP1 */ + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + }, + + { /* DP0 */ + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 4, 7), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + }, +}; + +const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { + .Flags = DESCRIPTOR_TERMINATE_LIST, + .SocketId = 0, + .PciePortList = PortList, + .DdiLinkList = DdiList +}; + +/*---------------------------------------------------------------------------------------*/ +/** + * OemCustomizeInitEarly + * + * Description: + * This stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity + * + * Parameters: + * @param[in] *InitEarly + * + * @retval VOID + * + **/ +/*---------------------------------------------------------------------------------------*/ +VOID +OemCustomizeInitEarly ( + IN OUT AMD_EARLY_PARAMS *InitEarly + ) +{ + InitEarly->GnbConfig.PcieComplexList = &PcieComplex; +} diff --git a/src/mainboard/amd/lamar/acpi/AmdImc.asl b/src/mainboard/amd/lamar/acpi/AmdImc.asl new file mode 100644 index 0000000..81dfb46 --- /dev/null +++ b/src/mainboard/amd/lamar/acpi/AmdImc.asl @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +OperationRegion(IMIO, SystemIO, 0x3E, 0x02) +Field(IMIO , ByteAcc, NoLock, Preserve) { + IMCX,8, + IMCA,8 +} + +IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) { + Offset(0x80), + MSTI, 8, + MITS, 8, + MRG0, 8, + MRG1, 8, + MRG2, 8, + MRG3, 8, +} + +Method(WACK, 0) +{ + Store(0, Local0) + Store(50, Local1) + While (LAnd (LNotEqual(Local0, 0xFA), LGreater(Local1,0))) { + Store(MRG0, Local0) + Sleep(10) + Decrement(Local1) + } +} + +//Init +Method (ITZE, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(0, MRG1) + Store(0, MRG2) + Store(0x80, MSTI) + WACK() + + Or(MRG2, 0x01, Local0) + + Store(0, MRG0) + Store(0, MRG1) + Store(Local0, MRG2) + Store(0x81, MSTI) + WACK() +} + +//Sleep +Method (IMSP, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(1, MRG1) + Store(0, MRG2) + Store(0x98, MSTI) + WACK() + + Store(0, MRG0) + Store(0xB4, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() +} + +//Wake +Method (IMWK, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(0, MRG1) + Store(0, MRG2) + Store(0x80, MSTI) + WACK() + + Or(MRG2, 0x01, Local0) + + Store(0, MRG0) + Store(0, MRG1) + Store(Local0, MRG2) + Store(0x81, MSTI) + WACK() +} diff --git a/src/mainboard/amd/lamar/acpi/gpe.asl b/src/mainboard/amd/lamar/acpi/gpe.asl new file mode 100644 index 0000000..3ea1764 --- /dev/null +++ b/src/mainboard/amd/lamar/acpi/gpe.asl @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 - 2014 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Scope(_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\_GPE\_L00\n") */ + Notify(_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\_GPE\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\_GPE\_L09\n") */ + /* Notify (_TZ.TZ00, 0x80) */ + } + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\_GPE\_L0B\n") */ + Notify(_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\_GPE\_L10\n") */ + } + + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\_GPE\_L11\n") */ + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\_GPE\_L18\n") */ + Notify(_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(_SB.PCI0.PBR3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\_GPE\_L1B\n") */ + Notify(_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ diff --git a/src/mainboard/amd/lamar/acpi/mainboard.asl b/src/mainboard/amd/lamar/acpi/mainboard.asl new file mode 100644 index 0000000..33be113 --- /dev/null +++ b/src/mainboard/amd/lamar/acpi/mainboard.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 - 2014 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + /* Data to be patched by the BIOS during POST */ + /* FIXME the patching is not done yet! */ + /* Memory related values */ + Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ + Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ + Name(PBLN, 0x0) /* Length of BIOS area */ + + Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ + Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ + Name(HPBA, 0xFED00000) /* Base address of HPET table */ + + Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + + /* Some global data */ + Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSV, Ones) /* Assume nothing */ + Name(PMOD, One) /* Assume APIC */ + + /* AcpiGpe0Blk */ + OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) + Field(GP0B, ByteAcc, NoLock, Preserve) { + , 11, + USBS, 1, + } diff --git a/src/mainboard/amd/lamar/acpi/routing.asl b/src/mainboard/amd/lamar/acpi/routing.asl new file mode 100644 index 0000000..6b2bae6 --- /dev/null +++ b/src/mainboard/amd/lamar/acpi/routing.asl @@ -0,0 +1,231 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * 2013 - 2014 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + /* Routing is in System Bus scope */ + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - F15 Host Controller */ + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, 0x0C, 0 }, + Package(){0x0001FFFF, 1, INTH, 0 }, + Package(){0x0001FFFF, 2, INTG, 0 }, + Package(){0x0001FFFF, 3, INTF, 0 }, + + /* Bus 0, Dev 2 - NB PCIe Gfx Bridge */ + Package(){0x0002FFFF, 0, INTE, 0 }, + Package(){0x0002FFFF, 1, INTF, 0 }, + Package(){0x0002FFFF, 2, INTG, 0 }, + Package(){0x0002FFFF, 3, INTH, 0 }, + + /* Bus 0, Dev 3 - NB GPP PCIe bridge */ + Package(){0x0003FFFF, 0, INTE, 0 }, + Package(){0x0003FFFF, 1, INTF, 0 }, + Package(){0x0003FFFF, 2, INTG, 0 }, + Package(){0x0003FFFF, 3, INTH, 0 }, + + /* Bus 0, Dev 4 - UMI Bridge */ + Package(){0x0004FFFF, 0, INTE, 0 }, + Package(){0x0004FFFF, 1, INTF, 0 }, + Package(){0x0004FFFF, 2, INTG, 0 }, + Package(){0x0004FFFF, 3, INTH, 0 }, + + /* SB devices */ + /* Bus 0, Dev 16 - USB: xHCI @ func 0 + * xHCI @ func 2 */ + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTC, 0 }, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, + + /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 + * EHCI @ func 2 */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ + Package(){0x0014FFFF, 1, INTB, 0 }, /* IDE Controller */ + Package(){0x0014FFFF, 0, INTA, 0 }, /* Azalia Audio Controller */ + Package(){0x0014FFFF, 2, INTC, 0 }, /* USB #4 OHCI Controller */ + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 2, INTB, 0 }, + + /* Bus 0, Dev 21 SB GPP Pcie Bridge */ + Package(){0x0015FFFF, 0, INTE, 0 }, + Package(){0x0015FFFF, 1, INTF, 0 }, + Package(){0x0015FFFF, 2, INTG, 0 }, + Package(){0x0015FFFF, 3, INTH, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - F15 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, 0, 12 }, + Package(){0x0001FFFF, 1, 0, 5 }, + + /* Bus 0, Dev 2 - PCIe Bridge for GFX slots */ + Package(){0x0002FFFF, 0, 0, 20 }, + Package(){0x0002FFFF, 1, 0, 21 }, + Package(){0x0002FFFF, 2, 0, 22 }, + Package(){0x0002FFFF, 3, 0, 23 }, + + /* Bus 0, Dev 3 - PCIe Bridge for NB GPP slots */ + Package(){0x0003FFFF, 0, 0, 20 }, + Package(){0x0003FFFF, 1, 0, 21 }, + Package(){0x0003FFFF, 2, 0, 22 }, + Package(){0x0003FFFF, 3, 0, 23 }, + + /* Bus 0, Dev 4 - UMI Bridge */ + + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + Package(){0x0014FFFF, 1, 0, 17 }, /* IDE Controller */ + Package(){0x0014FFFF, 0, 0, 16 }, /* Azalia Audio Controller */ + Package(){0x0014FFFF, 2, 0, 18 }, /* USB #4 OHCI Controller */ + + /* SB devices in APIC mode */ + /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 + * EHCI @ func 2 */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, 0, 18}, + Package(){0x0010FFFF, 1, 0, 18}, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, + + /* Bus0, Dev 21 PCIE Bridge */ + Package(){0x0015FFFF, 0, 0, 20 }, + Package(){0x0015FFFF, 1, 0, 21 }, + Package(){0x0015FFFF, 2, 0, 22 }, + Package(){0x0015FFFF, 3, 0, 23 }, + }) + + Name(PS2, Package(){ + /* The external GFX - Hooked to NB Gfx PCIe slots */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS2, Package(){ + /* The external GFX - Hooked to NB Gfx PCIe slots */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS3, Package(){ + /* PCIe slot - Hooked to NB GPP PCIe slots */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APS3, Package(){ + /* PCIe slot - Hooked to NB GPP PCIe slots */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PE0, Package(){ + /* PCIe slot - Hooked to PCIe Bridge 0*/ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APE0, Package(){ + /* PCIe slot - Hooked to PCIe Bridge 0*/ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PE1, Package(){ + /* PCIe slot - Hooked to PCIe Bridge 1*/ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APE1, Package(){ + /* PCIe slot - Hooked to PCIe Bridge 1*/ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PE2, Package(){ + /* PCIe slot - Hooked to PCIe Bridge 2*/ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APE2, Package(){ + /* PCIe slot - Hooked to PCIe Bridge 2*/ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PE3, Package(){ + /* PCIe slot - Hooked to PCIe Bridge 3 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APE3, Package(){ + /* PCIe slot - Hooked to PCIe Bridge 3*/ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + /* SB PCI Bridge */ + Name(PCIB, Package(){ + /* PCI slots: slot 0 behind Dev14, Fun4. */ + Package(){0x0005FFFF, 0, 0, 0x14 }, + Package(){0x0005FFFF, 1, 0, 0x15 }, + Package(){0x0005FFFF, 2, 0, 0x16 }, + Package(){0x0005FFFF, 3, 0, 0x17 }, + }) diff --git a/src/mainboard/amd/lamar/acpi/sata.asl b/src/mainboard/amd/lamar/acpi/sata.asl new file mode 100644 index 0000000..f675323 --- /dev/null +++ b/src/mainboard/amd/lamar/acpi/sata.asl @@ -0,0 +1 @@ +/* No SATA functionality */ diff --git a/src/mainboard/amd/lamar/acpi/si.asl b/src/mainboard/amd/lamar/acpi/si.asl new file mode 100644 index 0000000..aa49616 --- /dev/null +++ b/src/mainboard/amd/lamar/acpi/si.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 - 2014 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + Scope(_SI) { + Method(_SST, 1) { + /* DBGO("\_SI\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } + } /* End Scope SI */ + + diff --git a/src/mainboard/amd/lamar/acpi/sleep.asl b/src/mainboard/amd/lamar/acpi/sleep.asl new file mode 100644 index 0000000..fcce35e --- /dev/null +++ b/src/mainboard/amd/lamar/acpi/sleep.asl @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 - 2014 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* _PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ +Method(_PTS, 1) { + /* DBGO("\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(_SB.SBRI, 0x13)) { + * Store(0,_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + + Store (0x07, UPWS) +} /* End Method(_PTS) */ + +/* +* _BFS OEM Back From Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +*/ +Method(_BFS, 1) { + /* DBGO("\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ +} + +/* +* _WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(_WAK, 1) { + /* DBGO("\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* Re-enable HPET */ + Store(1,USBS) + + Return(WKST) +} /* End Method(_WAK) */ diff --git a/src/mainboard/amd/lamar/acpi/superio.asl b/src/mainboard/amd/lamar/acpi/superio.asl new file mode 100644 index 0000000..69c6108 --- /dev/null +++ b/src/mainboard/amd/lamar/acpi/superio.asl @@ -0,0 +1 @@ +/* No Super I/O device or functionality yet */ diff --git a/src/mainboard/amd/lamar/acpi/thermal.asl b/src/mainboard/amd/lamar/acpi/thermal.asl new file mode 100644 index 0000000..edb1daf --- /dev/null +++ b/src/mainboard/amd/lamar/acpi/thermal.asl @@ -0,0 +1 @@ +/* No thermal zone functionality */ diff --git a/src/mainboard/amd/lamar/acpi/usb_oc.asl b/src/mainboard/amd/lamar/acpi/usb_oc.asl new file mode 100644 index 0000000..394f201 --- /dev/null +++ b/src/mainboard/amd/lamar/acpi/usb_oc.asl @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2013 - 2014 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) diff --git a/src/mainboard/amd/lamar/acpi_tables.c b/src/mainboard/amd/lamar/acpi_tables.c new file mode 100644 index 0000000..1de3df9 --- /dev/null +++ b/src/mainboard/amd/lamar/acpi_tables.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <northbridge/amd/pi/agesawrapper.h> + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <cpu/amd/amdfam15.h> + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write southbridge IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, + IO_APIC_ADDR, 0); + + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1, + 0xFEC20000, 24); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edge-triggered, Active high */ + + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); + /* 1: LINT1 connect to NMI */ + + return current; +} diff --git a/src/mainboard/amd/lamar/agesawrapper.c b/src/mainboard/amd/lamar/agesawrapper.c new file mode 100644 index 0000000..dfdb481 --- /dev/null +++ b/src/mainboard/amd/lamar/agesawrapper.c @@ -0,0 +1,661 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <AGESA.h> +#include <cpu/amd/pi/s3_resume.h> +#include <cpu/x86/mtrr.h> +#include <cpuRegisters.h> +#include <FchPlatform.h> +#include <heapManager.h> +#include <northbridge/amd/pi/agesawrapper.h> +#include <northbridge/amd/pi/BiosCallOuts.h> + +VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr); +VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); + +#define FILECODE UNASSIGNED_FILE_FILECODE + +#ifndef __PRE_RAM__ +/* ACPI table pointers returned by AmdInitLate */ +static void *DmiTable = NULL; +static void *AcpiPstate = NULL; +static void *AcpiSrat = NULL; +static void *AcpiSlit = NULL; + +static void *AcpiWheaMce = NULL; +static void *AcpiWheaCmc = NULL; +static void *AcpiAlib = NULL; +static void *AcpiIvrs = NULL; +static void *AcpiCrat = NULL; +#endif /* #ifndef __PRE_RAM__ */ + +AGESA_STATUS agesawrapper_amdinitcpuio(void) +{ + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* Enable legacy video routing: D18F1xF4 VGA Enable */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); + PciData = 1; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* The platform BIOS needs to ensure the memory ranges of southbridge legacy + * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are + * set to non-posted regions. + */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); + PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ + PciData |= 1 << 7; /* set NP (non-posted) bit */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); + PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Map the remaining PCI hole as posted MMIO */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); + PciData = 0x00FECF00; /* last address before non-posted range */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); + MsrReg = (MsrReg >> 8) | 3; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); + PciData = (UINT32)MsrReg; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Send all IO (0000-FFFF) to southbridge. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); + PciData = 0x0000F000; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); + PciData = 0x00000003; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + Status = AGESA_SUCCESS; + return Status; +} + +AGESA_STATUS agesawrapper_amdinitmmio(void) +{ + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* + Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base + Address MSR register. + */ + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; + LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); + + /* + Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + */ + LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); + MsrReg = MsrReg | 0x0000400000000000; + LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); + + /* For serial port */ + PciData = 0xFF03FFD5; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set ROM cache onto WP to decrease post time */ + MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; + LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; + LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); + + Status = AGESA_SUCCESS; + return Status; +} + +AGESA_STATUS agesawrapper_amdinitreset(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESET_PARAMS AmdResetParams; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + LibAmdMemFill (&AmdResetParams, + 0, + sizeof (AMD_RESET_PARAMS), + &(AmdResetParams.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; + AmdParamStruct.AllocationMethod = ByHost; + AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); + AmdParamStruct.NewStructPtr = &AmdResetParams; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdResetParams.FchInterface.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + AmdResetParams.FchInterface.Xhci1Enable = TRUE; + + AmdResetParams.FchInterface.SataEnable = !(IS_ENABLED(CONFIG_HUDSON_SATA_IDE) || IS_ENABLED(CONFIG_HUDSON_SATA_LEGACY_IDE)); + AmdResetParams.FchInterface.IdeEnable = (IS_ENABLED(CONFIG_HUDSON_SATA_IDE) || IS_ENABLED(CONFIG_HUDSON_SATA_LEGACY_IDE)); + + status = AmdInitReset(&AmdResetParams); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + return status; +} + +AGESA_STATUS agesawrapper_amdinitearly(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_EARLY_PARAMS *AmdEarlyParamsPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; + OemCustomizeInitEarly (AmdEarlyParamsPtr); + + status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + + return status; +} + +AGESA_STATUS agesawrapper_amdinitpost(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_POST_PARAMS *PostParams; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = NULL; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; + + // Do not use IS_ENABLED here. CONFIG_GFXUMA should always have a value. Allow + // the compiler to flag the error if CONFIG_GFXUMA is not set. + PostParams->MemConfig.UmaMode = CONFIG_GFXUMA ? UMA_AUTO : UMA_NONE; + PostParams->MemConfig.UmaSize = 0; + status = AmdInitPost (PostParams); + printk( + BIOS_SPEW, + "setup_uma_memory: umamode %s\n", + (PostParams->MemConfig.UmaMode == UMA_AUTO) ? "UMA_AUTO" : + (PostParams->MemConfig.UmaMode == UMA_SPECIFIED) ? "UMA_SPECIFIED" : + (PostParams->MemConfig.UmaMode == UMA_NONE) ? "UMA_NONE" : + "unknown" + ); + printk( + BIOS_SPEW, + "setup_uma_memory: syslimit 0x%08llX, bottomio 0x%08lx\n", + (unsigned long long)(PostParams->MemConfig.SysLimit) << 16, + (unsigned long)(PostParams->MemConfig.BottomIo) << 16 + ); + printk( + BIOS_SPEW, + "setup_uma_memory: uma size %luMB, uma start 0x%08lx\n", + (unsigned long)(PostParams->MemConfig.UmaSize) >> (20 - 16), + (unsigned long)(PostParams->MemConfig.UmaBase) << 16 + ); + + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + /* Initialize heap space */ + EmptyHeap(); + + return status; +} + +AGESA_STATUS agesawrapper_amdinitenv(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_ENV_PARAMS *EnvParam; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + status = AmdCreateStruct (&AmdParamStruct); + EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; + + EnvParam->FchInterface.AzaliaController = AzEnable; + EnvParam->FchInterface.SataClass = CONFIG_HUDSON_SATA_MODE; + EnvParam->FchInterface.SataEnable = !(IS_ENABLED(CONFIG_HUDSON_SATA_IDE) || IS_ENABLED(CONFIG_HUDSON_SATA_LEGACY_IDE)); + EnvParam->FchInterface.IdeEnable = (IS_ENABLED(CONFIG_HUDSON_SATA_IDE) || IS_ENABLED(CONFIG_HUDSON_SATA_LEGACY_IDE)); + EnvParam->FchInterface.SataIdeMode = IS_ENABLED(CONFIG_HUDSON_SATA_LEGACY_IDE); + EnvParam->GnbEnvConfiguration.IommuSupport = FALSE; + + status = AmdInitEnv (EnvParam); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(EnvParam->StdHeader.HeapStatus); + /* Initialize Subordinate Bus Number and Secondary Bus Number + * In platform BIOS this address is allocated by PCI enumeration code + Modify D1F0x18 + */ + + return status; +} + +#ifndef __PRE_RAM__ +VOID* agesawrapper_getlateinitptr (int pick) +{ + switch (pick) { + case PICK_DMI: + return DmiTable; + case PICK_PSTATE: + return AcpiPstate; + case PICK_SRAT: + return AcpiSrat; + case PICK_SLIT: + return AcpiSlit; + case PICK_WHEA_MCE: + return AcpiWheaMce; + case PICK_WHEA_CMC: + return AcpiWheaCmc; + case PICK_ALIB: + return AcpiAlib; + case PICK_IVRS: + return AcpiIvrs; + case PICK_CRAT: + return AcpiCrat; + default: + return NULL; + } +} +#endif /* #ifndef __PRE_RAM__ */ + +AGESA_STATUS agesawrapper_amdinitmid(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_MID_PARAMS *MidParam; + + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio (); + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + MidParam = (AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr; + + MidParam->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + MidParam->GnbMidConfiguration.GnbIoapicAddress = 0xFEC20000; + + MidParam->FchInterface.AzaliaController = AzEnable; + MidParam->FchInterface.SataClass = CONFIG_HUDSON_SATA_MODE; + MidParam->FchInterface.SataEnable = !(IS_ENABLED(CONFIG_HUDSON_SATA_IDE) || IS_ENABLED(CONFIG_HUDSON_SATA_LEGACY_IDE)); + MidParam->FchInterface.IdeEnable = (IS_ENABLED(CONFIG_HUDSON_SATA_IDE) || IS_ENABLED(CONFIG_HUDSON_SATA_LEGACY_IDE)); + MidParam->FchInterface.SataIdeMode = IS_ENABLED(CONFIG_HUDSON_SATA_LEGACY_IDE); + + status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + + return status; +} + +#ifndef __PRE_RAM__ +AGESA_STATUS agesawrapper_amdinitlate(void) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_LATE_PARAMS *AmdLateParams; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */ + AmdCreateStruct(&AmdParamStruct); + AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; + Status = AmdInitLate(AmdLateParams); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(AmdLateParams->StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + } + + DmiTable = AmdLateParams->DmiTable; + AcpiPstate = AmdLateParams->AcpiPState; + AcpiSrat = AmdLateParams->AcpiSrat; + AcpiSlit = AmdLateParams->AcpiSlit; + + AcpiWheaMce = AmdLateParams->AcpiWheaMce; + AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; + AcpiAlib = AmdLateParams->AcpiAlib; + AcpiIvrs = AmdLateParams->AcpiIvrs; + AcpiCrat = AmdLateParams->AcpiCrat; + + printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x," + "AcpiSlit:%x, Mce:%x, Cmc:%x," + "Alib:%x, AcpiIvrs:%x in %s\n", + (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, + (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, + (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__); + + /* AmdReleaseStruct (&AmdParamStruct); */ + return Status; +} +#endif /* #ifndef __PRE_RAM__ */ + +AGESA_STATUS agesawrapper_amdlaterunaptask ( + UINT32 Func, + UINT32 Data, + VOID *ConfigPtr + ) +{ + AGESA_STATUS Status; + AP_EXE_PARAMS ApExeParams; + + LibAmdMemFill (&ApExeParams, + 0, + sizeof (AP_EXE_PARAMS), + &(ApExeParams.StdHeader)); + + ApExeParams.StdHeader.AltImageBasePtr = 0; + ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + ApExeParams.StdHeader.Func = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.FunctionNumber = Func; + ApExeParams.RelatedDataBlock = ConfigPtr; + + Status = AmdLateRunApTask (&ApExeParams); + if (Status != AGESA_SUCCESS) { + /* agesawrapper_amdreadeventlog(); */ + ASSERT(Status == AGESA_SUCCESS); + } + + return Status; +} + +#if CONFIG_HAVE_ACPI_RESUME + +AGESA_STATUS agesawrapper_amdinitresume(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESUME_PARAMS *AmdResumeParamsPtr; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; + + AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; + AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeNonVolatile; + OemAgesaGetS3Info (S3DataType, + (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize, + (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage); + + status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); + + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + + return status; +} + +#ifndef __PRE_RAM__ +AGESA_STATUS agesawrapper_fchs3earlyrestore(void) +{ + AGESA_STATUS status = AGESA_SUCCESS; + + FCH_DATA_BLOCK FchParams; + AMD_CONFIG_PARAMS StdHeader; + + StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; + StdHeader.AltImageBasePtr = 0; + StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + StdHeader.Func = 0; + StdHeader.ImageBasePtr = 0; + + LibAmdMemFill (&FchParams, + 0, + sizeof (FchParams), + &StdHeader); + + FchParams.StdHeader = &StdHeader; + s3_resume_init_data(&FchParams); + + FchInitS3EarlyRestore(&FchParams); + + return status; +} +#endif /* #ifndef __PRE_RAM__ */ + +AGESA_STATUS agesawrapper_amds3laterestore(void) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + AMD_S3LATE_PARAMS AmdS3LateParams; + AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; + S3_DATA_TYPE S3DataType; + + agesawrapper_amdinitcpuio(); + LibAmdMemFill (&AmdS3LateParams, + 0, + sizeof (AMD_S3LATE_PARAMS), + &(AmdS3LateParams.StdHeader)); + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.AllocationMethod = ByHost; + AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; + AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdS3LateParamsPtr = &AmdS3LateParams; + AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS); + + AmdCreateStruct (&AmdInterfaceParams); + + AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeVolatile; + + OemAgesaGetS3Info (S3DataType, + (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, + (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); + + Status = AmdS3LateRestore (AmdS3LateParamsPtr); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + } + + return Status; +} + +#ifndef __PRE_RAM__ + +AGESA_STATUS agesawrapper_fchs3laterestore(void) +{ + AGESA_STATUS status = AGESA_SUCCESS; + + AMD_CONFIG_PARAMS StdHeader; + FCH_DATA_BLOCK FchParams; + + StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; + StdHeader.AltImageBasePtr = 0; + StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + StdHeader.Func = 0; + StdHeader.ImageBasePtr = 0; + + LibAmdMemFill (&FchParams, + 0, + sizeof (FchParams), + &StdHeader); + + FchParams.StdHeader = &StdHeader; + s3_resume_init_data(&FchParams); + FchInitS3LateRestore(&FchParams); + + return status; +} + +AGESA_STATUS agesawrapper_amdS3Save(void) +{ + AGESA_STATUS Status; + AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdInterfaceParams, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdInterfaceParams.StdHeader)); + + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdInterfaceParams.AllocationMethod = PostMemDram; + AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; + AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; + AmdInterfaceParams.StdHeader.Func = 0; + + AmdCreateStruct(&AmdInterfaceParams); + AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; + AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; + + Status = AmdS3Save(AmdS3SaveParamsPtr); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + } + + S3DataType = S3DataTypeNonVolatile; + printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + + Status = OemAgesaSaveS3Info ( + S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + + printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); + + if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { + S3DataType = S3DataTypeVolatile; + + Status = OemAgesaSaveS3Info ( + S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); + } + OemAgesaSaveMtrr(); + + AmdReleaseStruct (&AmdInterfaceParams); + + return Status; +} + +#endif /* #ifndef __PRE_RAM__ */ +#endif /* CONFIG_HAVE_ACPI_RESUME */ + +AGESA_STATUS agesawrapper_amdreadeventlog (UINT8 HeapStatus) +{ + AGESA_STATUS Status; + EVENT_PARAMS AmdEventParams; + + LibAmdMemFill (&AmdEventParams, + 0, + sizeof (EVENT_PARAMS), + &(AmdEventParams.StdHeader)); + + AmdEventParams.StdHeader.AltImageBasePtr = 0; + AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdEventParams.StdHeader.Func = 0; + AmdEventParams.StdHeader.ImageBasePtr = 0; + AmdEventParams.StdHeader.HeapStatus = HeapStatus; + Status = AmdReadEventLog (&AmdEventParams); + while (AmdEventParams.EventClass != 0) { + printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo); + printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2); + printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); + Status = AmdReadEventLog (&AmdEventParams); + } + + return Status; +} diff --git a/src/mainboard/amd/lamar/board_info.txt b/src/mainboard/amd/lamar/board_info.txt new file mode 100644 index 0000000..8bce92e --- /dev/null +++ b/src/mainboard/amd/lamar/board_info.txt @@ -0,0 +1,5 @@ +Board name: DB-FP3 (Lamar) +Category: eval +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/amd/lamar/cmos.layout b/src/mainboard/amd/lamar/cmos.layout new file mode 100644 index 0000000..5520564 --- /dev/null +++ b/src/mainboard/amd/lamar/cmos.layout @@ -0,0 +1,114 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +#***************************************************************************** + +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/amd/lamar/devicetree.cb b/src/mainboard/amd/lamar/devicetree.cb new file mode 100644 index 0000000..eb41942 --- /dev/null +++ b/src/mainboard/amd/lamar/devicetree.cb @@ -0,0 +1,118 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# 2013 - 2014 Sage Electronic Engineering, LLC +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +chip northbridge/amd/pi/00630F01/root_complex + device cpu_cluster 0 on + chip cpu/amd/pi/00630F01 + device lapic 10 on end + end + end + + device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/pi/00630F01 # CPU side of HT root complex + + chip northbridge/amd/pi/00630F01 # PCI side of HT root complex + device pci 0.0 on end # 0x1422 Root Complex + device pci 0.2 off end # 0x1423 IOMMU + device pci 1.0 on end # 0x13XX Internal Graphics + device pci 1.1 on end # 0x1308 DisplayPort/HDMI Audio + device pci 2.0 on end # 0x1424 GFX PCIe Host Bridge + device pci 2.1 on end # 0x1425 P2P Bridge for GFX PCIe Port 0 (PCIe x16 slot J119) + device pci 2.2 off end # 0x1425 P2P Bridge for GFX PCIe Port 1 + device pci 3.0 on end # 0x1424 GPP PCIe Host Bridge + device pci 3.1 on end # 0x1426 P2P Bridge for GPP PCIe Port 0 (PCIe x4 slot J118) + device pci 3.2 on end # 0x1426 P2P Bridge for GPP PCIe Port 1 (PCIe x4 slot J120) + device pci 3.3 off end # 0x1426 P2P Bridge for GPP PCIe Port 2 + device pci 3.4 off end # 0x1426 P2P Bridge for GPP PCIe Port 3 + device pci 3.5 off end # 0x1426 P2P Bridge for GPP PCIe Port 4 + device pci 4.0 on end # 0x1424 UMI PCIe Host Bridge +# device pci 4.1 on end # 0x1426 P2P bridge for UMI link +# device pci 4.2 off end # 0x1426 Virtual P2P bridge for SB PCIe Port 3 +# device pci 4.3 off end # 0x1426 Virtual P2P bridge for SB PCIe Port 2 +# device pci 4.4 off end # 0x1426 Virtual P2P bridge for SB PCIe Port 1 +# device pci 4.5 off end # 0x1426 Virtual P2P bridge for SB PCIe Port 0 + end #chip northbridge/amd/pi/00630F01 + + chip southbridge/amd/pi/hudson + device pci 10.0 on end # 0x7814 XHCI HC0 + device pci 10.1 on end # 0x7814 XHCI HC1 + device pci 11.0 on end # 0x7800-0x7805 SATA (device ID depends on mode) + device pci 12.0 on end # 0x7807 USB OHCI + device pci 12.2 on end # 0x7808 USB EHCI + device pci 13.0 on end # 0x7807 USB OHCI + device pci 13.2 on end # 0x7808 USB EHCI + device pci 14.0 on # 0x780B SMBus + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # 0x780C IDE + device pci 14.2 on end # 0x780D HDA + device pci 14.3 on # 0x780E LPC + chip superio/fintek/f81216h + device pnp 4e.0 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 3 + end + device pnp 4e.1 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 4 + end + device pnp 4e.2 off end # COM3 + device pnp 4e.3 off end # COM4 + device pnp 4e.8 off end # WDT + end # f81865f + end #LPC + device pci 14.4 on end # 0x780F PCI :: PCI-b conflict with GPIO. + device pci 14.5 on end # 0x7809 USB OHCI + device pci 14.7 on end # 0x7806 SD Flash Controller + register "sd_mode" = "3" + device pci 15.0 on end # 0x43A0 SB GPP Port 0 (Integrated Realtek GbE Controller) + device pci 15.1 on end # 0x43A1 SB GPP Port 1 (mPCIe slot J122) + device pci 15.2 on end # 0x43A2 SB GPP Port 2 (mPCIe slot J123) + device pci 15.3 off end # 0x43A3 SB GPP Port 3 + register "gpp_configuration" = "4" + device pci 16.0 on end # 0x7809 USB OHCI (when the xHCI device is disabled) + end #southbridge/amd/pi/hudson + + device pci 18.0 on end # 0x141A HT Configuration + device pci 18.1 on end # 0x141B Address Maps + device pci 18.2 on end # 0x141C DRAM Configuration + device pci 18.3 on end # 0x141D Miscellaneous + device pci 18.4 on end # 0x141E Power Management + device pci 18.5 on end # 0x141F Northbridge + + register "spdAddrLookup" = " + { + { {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + }" + + end #chip northbridge/amd/pi/00630F01 # CPU side of HT root complex + end #domain +end #northbridge/amd/pi/00630F01/root_complex diff --git a/src/mainboard/amd/lamar/dsdt.asl b/src/mainboard/amd/lamar/dsdt.asl new file mode 100644 index 0000000..dcf164b --- /dev/null +++ b/src/mainboard/amd/lamar/dsdt.asl @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2013 - 2014 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ + + /* Globals for the platform */ + #include "acpi/mainboard.asl" + + /* Describe the USB Overcurrent pins */ + #include "acpi/usb_oc.asl" + + /* PCI IRQ mapping for the Southbridge */ + #include <southbridge/amd/pi/hudson/acpi/pcie.asl> + + /* Describe the processor tree (_PR) */ + #include <cpu/amd/pi/00630F01/acpi/cpu.asl> + + /* Contains the supported sleep states for this chipset */ + #include <southbridge/amd/pi/hudson/acpi/sleepstates.asl> + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" + + /* System Bus */ + Scope(_SB) { /* Start _SB scope */ + /* global utility methods expected within the _SB scope */ + #include <arch/x86/acpi/globutil.asl> + + /* Describe IRQ Routing mapping for this platform (within the _SB scope) */ + #include "acpi/routing.asl" + + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + + Device(PCI0) { + /* Describe the AMD Northbridge */ + #include <northbridge/amd/pi/00630F01/acpi/northbridge.asl> + + /* Describe the AMD Fusion Controller Hub Southbridge */ + #include <southbridge/amd/pi/hudson/acpi/fch.asl> + } + + /* Describe PCI INT[A-H] for the Southbridge */ + #include <southbridge/amd/pi/hudson/acpi/pci_int.asl> + + } /* End _SB scope */ + + /* Describe SMBUS for the Southbridge */ + #include <southbridge/amd/pi/hudson/acpi/smbus.asl> + + /* Define the General Purpose Events for the platform */ + #include "acpi/gpe.asl" + + /* Define the Thermal zones and methods for the platform */ + #include "acpi/thermal.asl" + + /* Define the System Indicators for the platform */ + #include "acpi/si.asl" +} +/* End of ASL file */ diff --git a/src/mainboard/amd/lamar/get_bus_conf.c b/src/mainboard/amd/lamar/get_bus_conf.c new file mode 100644 index 0000000..5d03cb5 --- /dev/null +++ b/src/mainboard/amd/lamar/get_bus_conf.c @@ -0,0 +1,150 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> +#include <stdint.h> +#include <stdlib.h> +#include <cpu/amd/amdfam15.h> +#include <northbridge/amd/pi/agesawrapper.h> +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) +#include "imc.h" +#endif + +/* Global variables for MB layouts and these will be shared by irqtable mptable + * and acpi_tables busnum is default. + */ +u8 bus_isa; +u8 bus_sb[16]; +u32 apicid_sb, apicid_nb; + +/* + * Here you only need to set value in pci1234 for HT-IO that could be installed or not + * You may need to preset pci1234 for HTIO board, + * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + */ +u32 pci1234x[] = { + 0x0000ff0, +}; + +u32 bus_type[256]; +u32 sbdn_sb; + +static u32 get_bus_conf_done = 0; + +#if CONFIG_HAVE_ACPI_RESUME +extern u8 acpi_slp_type; +#endif +void get_bus_conf(void) +{ + u32 apicid_base; + u32 status; + + device_t dev; + int i, j; + + if (get_bus_conf_done == 1) + return; /* do it only once */ + + get_bus_conf_done = 1; + + /* + * This is the call to AmdInitLate. It is really in the wrong place, conceptually, + * but functionally within the coreboot model, this is the best place to make the + * call. The logically correct place to call AmdInitLate is after PCI scan is done, + * after the decision about S3 resume is made, and before the system tables are + * written into RAM. The routine that is responsible for writing the tables is + * "write_tables", called near the end of "hardwaremain". There is no platform + * specific entry point between the S3 resume decision point and the call to + * "write_tables", and the next platform specific entry points are the calls to + * the ACPI table write functions. The first of ose would seem to be the right + * place, but other table write functions, e.g. the PIRQ table write function, are + * called before the ACPI tables are written. This routine is called at the beginning + * of each of the write functions called prior to the ACPI write functions, so this + * becomes the best place for this call. + */ +#if CONFIG_HAVE_ACPI_RESUME + if (acpi_slp_type != 3) { + status = agesawrapper_amdinitlate(); + if(status) { + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); + } + status = agesawrapper_amdS3Save(); + if (status) { + printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status); + } + } +#else + status = agesawrapper_amdinitlate(); + if (status) + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); +#endif + +// setup_ioapic(0xFEC20000, 5); +// dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ +// pci_write_config32(dev, 0xF8, 0); +// pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ + + sbdn_sb = 0; + + memset(bus_sb, 0, sizeof(bus_sb)); + + for (i = 0; i < 256; i++) { + bus_type[i] = 0; /* default ISA bus. */ + } + + bus_type[0] = 1; /* pci */ + + bus_sb[0] = (pci1234x[0] >> 16) & 0xff; + + /* Hudson */ + dev = dev_find_slot(bus_sb[0], PCI_DEVFN(sbdn_sb + 0x14, 4)); + + if (dev) { + bus_sb[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + for (j = bus_sb[1]; j < bus_isa; j++) + bus_type[j] = 1; + } + + for (i = 0; i < 12; i++) { + dev = dev_find_slot(bus_sb[0], PCI_DEVFN(sbdn_sb + 0x14, i)); + if (dev) { + bus_sb[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + } + } + for (j = bus_sb[2]; j < bus_isa; j++) + bus_type[j] = 1; + + /* I/O APICs: APIC ID Version State Address */ + bus_isa = 10; + apicid_base = CONFIG_MAX_CPUS; + apicid_sb = apicid_base; + +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) + /* AMD AGESA does not enable thermal zone, so we enable it here. */ + enable_imc_thermal_zone(); +#endif +} diff --git a/src/mainboard/amd/lamar/irq_tables.c b/src/mainboard/amd/lamar/irq_tables.c new file mode 100644 index 0000000..dc457cc --- /dev/null +++ b/src/mainboard/amd/lamar/irq_tables.c @@ -0,0 +1,112 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> +#include <cpu/amd/amdfam15.h> + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +extern u8 bus_isa; +extern u8 bus_sb[6]; +extern unsigned long sbdn_sb; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = bus_sb[0]; + pirq->rtr_devfn = ((sbdn_sb + 0x14) << 3) | 4; + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* pci bridge */ + write_pirq_info(pirq_info, bus_sb[0], ((sbdn_sb + 0x14) << 3) | 4, + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; +} diff --git a/src/mainboard/amd/lamar/mainboard.c b/src/mainboard/amd/lamar/mainboard.c new file mode 100644 index 0000000..4bde7a6 --- /dev/null +++ b/src/mainboard/amd/lamar/mainboard.c @@ -0,0 +1,208 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <arch/acpi.h> +#include <northbridge/amd/pi/BiosCallOuts.h> +#include <cpu/amd/pi/s3_resume.h> +#include <northbridge/amd/pi/agesawrapper.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <northbridge/amd/pi/00630F01/pci_devs.h> +#include <southbridge/amd/pi/hudson/amd_pci_int_defs.h> +#include <southbridge/amd/pi/hudson/hudson.h> +#include <southbridge/amd/pi/hudson/pci_devs.h> +#include <southbridge/amd/amd_pci_util.h> + +/*********************************************************** + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + * + * These values are used by the PCI configuration space, + * MP Tables. TODO: Make ACPI use these values too. + */ +const u8 mainboard_picr_data[] = { +#if defined(__GNUC__) + [0 ... FCH_INT_TABLE_SIZE-1] = 0x1F, +#endif + /* + * [80..81] Northbridge devices (these indicies are beyond + * the southbridge C00/C01 range) + */ + [PIRQ_GFX] = 0x0C, + [PIRQ_ACTL] = 0x1F, + /* [00..07] INTA# - INTH# */ + [PIRQ_A] = 0x0A, + [PIRQ_B] = 0x0B, + [PIRQ_C] = 0x0A, + [PIRQ_D] = 0x0B, + [PIRQ_E] = 0x0A, + [PIRQ_F] = 0x0B, + [PIRQ_G] = 0x0A, + [PIRQ_H] = 0x0B, + /* [08..0B] MISC, MISC0, MISC1 (HPET lower bits), MISC2 (HPET upper bits) */ + [PIRQ_MISC] = 0xFA, + [PIRQ_MISC0] = 0xF1, + [PIRQ_MISC1] = 0x00, /* HPET lower bits */ + [PIRQ_MISC2] = 0x00, /* HPET upper bits */ + /* [0C..0F] INT from Serial irq */ + /* [10..1F] SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */ +// [PIRQ_SD] = 0x0E, + /* [20..25] IMC INT0 - 5 */ + /* [30..37] USB Devs 18/19/22/20 INTA-C */ + [PIRQ_EHCI1] = 0x0A, + [PIRQ_OHCI1] = 0x0B, + [PIRQ_EHCI2] = 0x0A, + [PIRQ_OHCI2] = 0x0B, + [PIRQ_EHCI3] = 0x0A, + [PIRQ_OHCI3] = 0x0B, + [PIRQ_OHCI4] = 0x0B, + /* [40..41] IDE, SATA */ + [PIRQ_IDE] = 0x0A, + [PIRQ_SATA] = 0x09, + /* [50..57] GPPInt0 - 3 */ + [PIRQ_GPP0] = 0x0A, + [PIRQ_GPP1] = 0x0B, + [PIRQ_GPP2] = 0x0A, + [PIRQ_GPP3] = 0x0B, +}; + +const u8 mainboard_intr_data[] = { +#if defined(__GNUC__) + [0 ... FCH_INT_TABLE_SIZE-1] = 0x1F, +#endif + /* [80..81] Northbridge devices (indicies above C00/C01 range) */ + [PIRQ_GFX] = 0x0C, + [PIRQ_ACTL] = 0x10, + /* [00..07] INTA# - INTH# */ + [PIRQ_A] = 0x10, + [PIRQ_B] = 0x11, + [PIRQ_C] = 0x12, + [PIRQ_D] = 0x13, + [PIRQ_E] = 0x14, + [PIRQ_F] = 0x15, + [PIRQ_G] = 0x16, + [PIRQ_H] = 0x17, + /* [08..0B] Misc-nil,0,1,2, INT from Serial irq */ + [PIRQ_MISC] = 0x00, + [PIRQ_MISC0] = 0x00, + [PIRQ_MISC1] = 0x00, /* HPET lower bits */ + [PIRQ_MISC2] = 0x00, /* HPET upper bits */ + /* [0C..0F] INT from Serial irq */ + /* [10..1F] SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */ + [PIRQ_SCI] = 0x09, + [PIRQ_HDA] = 0x10, +// [PIRQ_SD] = 0x12, + /* [20..25] IMC INT0 - 5 */ + /* [30..37] USB Devs 18/19/22/20 INTA-C */ + [PIRQ_EHCI1] = 0x11, + [PIRQ_OHCI1] = 0x12, + [PIRQ_EHCI2] = 0x11, + [PIRQ_OHCI2] = 0x12, + [PIRQ_EHCI3] = 0x11, + [PIRQ_OHCI3] = 0x12, + [PIRQ_OHCI4] = 0x12, + /* [40..41] IDE, SATA */ + [PIRQ_IDE] = 0x11, + [PIRQ_SATA] = 0x13, + /* [50..57] GPPInt0 - 3 */ + [PIRQ_GPP0] = 0x10, + [PIRQ_GPP1] = 0x11, + [PIRQ_GPP2] = 0x12, + [PIRQ_GPP3] = 0x13, +}; + +/* + * This table defines the index into the picr/intr_data + * tables for each device. Any enabled device and slot + * that uses hardware interrupts should have an entry + * in this table to define its index into the FCH + * PCI_INTR register 0xC00/0xC01. This index will define + * the interrupt that it should use. Putting PIRQ_A into + * the PIN A index for a device will tell that device to + * use PIC IRQ 10 if it uses PIN A for its hardware INT. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ +// {GFX_DEVFN, {PIRQ_GFX, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ +// {ACTL_DEVFN, {PIRQ_NC, PIRQ_ACTL, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */ + {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe J119: 02.1 */ + {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe J118: 03.1 */ + {NB_PCIE_PORT4_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe J120: 03.2 */ + {XHCI_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */ + {XHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.1 */ + {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ + {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ + {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ + {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ + {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ + {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ + {IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}}, /* IDE: 14.1 */ + {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ + {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCI: 14.4 */ + {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4: 14.5 */ +// {SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */ + {SB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* LAN: 15.0 */ + {SB_PCIE_PORT2_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* mPCIe J122: 15.1 */ + {SB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* mPCIe J123: 15.2 */ + {SB_PCIE_PORT4_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* unused 15.3 */ + {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 (same device as xHCI 10.0) */ + {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 (same device as xHCI 10.1) */ +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = FCH_INT_TABLE_SIZE /* FIXME sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct) */; + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + +/************************************************* + * enable the dedicated function in lamar board. + *************************************************/ +static void mainboard_enable(device_t dev) +{ + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + /* + * The mainboard is the first place that we get control in ramstage. Check + * for S3 resume and call the approriate AGESA/CIMx resume functions. + */ +#if CONFIG_HAVE_ACPI_RESUME + acpi_slp_type = acpi_get_sleep_type(); + if (acpi_slp_type == 3) + agesawrapper_fchs3earlyrestore(); +#endif + + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/amd/lamar/mptable.c b/src/mainboard/amd/lamar/mptable.c new file mode 100644 index 0000000..e4e0d17 --- /dev/null +++ b/src/mainboard/amd/lamar/mptable.c @@ -0,0 +1,170 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <arch/io.h> +#include <string.h> +#include <stdint.h> +#include <cpu/amd/amdfam15.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include <southbridge/amd/amd_pci_util.h> +#include <drivers/generic/ioapic/chip.h> +#include <arch/ioapic.h> +#include <southbridge/amd/pi/hudson/amd_pci_int_defs.h> +#include <southbridge/amd/pi/hudson/pci_devs.h> +#include <northbridge/amd/pi/00630F01/pci_devs.h> + +extern u8 bus_sb[16]; +extern u32 bus_type[256]; +extern u32 sbdn_sb; +extern u32 apicid_nb, apicid_sb; + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + u32 apicver_nb, apicver_sb; + + /* Intialize the MP_Table */ + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + + /* + * Type 0: Processor Entries: + * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, + * CPU Signature (Stepping, Model, Family), + * Feature Flags + */ + smp_write_processors(mc); + + /* Get Bus Configuration */ + get_bus_conf(); + + /* + * Type 1: Bus Entries: + * Bus ID, Bus Type + */ + mptable_write_buses(mc, NULL, &bus_isa); + + /* + * Type 2: I/O APICs: + * APIC ID, Version, APIC Flags:EN, Address + */ + +#define NB_APIC_ADDR 0xFEC20000 + + apicid_nb = (io_apic_read(NB_APIC_ADDR, 0x00) >> 24); /* Get the GNB IOAPIC ID */ + apicver_nb = (io_apic_read(NB_APIC_ADDR, 0x01) & 0xFF); /* Get the GNB IOAPIC version */ + + smp_write_ioapic(mc, apicid_nb, apicver_nb, NB_APIC_ADDR); + + apicid_sb = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24); /* Get the southbridge IOAPIC ID */ + apicver_sb = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF); /* Get the southbridge IOAPIC version */ + + smp_write_ioapic(mc, apicid_sb, apicver_sb, IO_APIC_ADDR); + + /* + * Type 3: I/O Interrupt Table Entries: + * Int Type, Int Polarity, Int Level, Source Bus ID, + * Source Bus IRQ, Dest APIC ID, Dest PIN# + */ + mptable_add_isa_interrupts(mc, bus_isa, apicid_nb, 0); + mptable_add_isa_interrupts(mc, bus_isa, apicid_sb, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, fn, apic, pin) \ + if (((pin) != 0x00) && ((pin) != 0x1F)) \ + { \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apic, (pin)); \ + } + + /* APU Internal Graphic Device */ + PCI_INT(0x0, 0x01, 0x0, apicid_nb, intr_data_ptr[PIRQ_GFX]); + PCI_INT(0x0, 0x01, 0x1, apicid_nb, intr_data_ptr[PIRQ_ACTL]); + + /* SMBUS / ACPI */ + PCI_INT(0x0, 0x14, 0x0, apicid_sb, intr_data_ptr[PIRQ_SMBUS]); + + /* Southbridge HD Audio */ + PCI_INT(0x0, 0x14, 0x2, apicid_sb, intr_data_ptr[PIRQ_HDA]); + + /* USB */ + PCI_INT(0x0, 0x12, 0x0, apicid_sb, intr_data_ptr[PIRQ_OHCI1]); + PCI_INT(0x0, 0x12, 0x2, apicid_sb, intr_data_ptr[PIRQ_EHCI1]); + PCI_INT(0x0, 0x13, 0x0, apicid_sb, intr_data_ptr[PIRQ_OHCI2]); + PCI_INT(0x0, 0x13, 0x2, apicid_sb, intr_data_ptr[PIRQ_EHCI2]); + PCI_INT(0x0, 0x16, 0x0, apicid_sb, intr_data_ptr[PIRQ_OHCI3]); + PCI_INT(0x0, 0x16, 0x2, apicid_sb, intr_data_ptr[PIRQ_EHCI3]); + PCI_INT(0x0, 0x14, 0x5, apicid_sb, intr_data_ptr[PIRQ_OHCI4]); + + /* SATA */ + PCI_INT(0x0, 0x11, 0x0, apicid_sb, intr_data_ptr[PIRQ_SATA]); + + /* IDE */ + PCI_INT(0x0, 0x14, 0x1, apicid_sb, intr_data_ptr[PIRQ_IDE]); + + /* PCI slots */ + /* NB Gfx PCIe Bridges */ + PCI_INT(0, 0x2, 0x1, apicid_nb, intr_data_ptr[PIRQ_A]); + PCI_INT(0, 0x2, 0x2, apicid_nb, intr_data_ptr[PIRQ_A]); + + /* NB GPP PCIe Bridges */ + PCI_INT(0, 0x3, 0x1, apicid_nb, intr_data_ptr[PIRQ_A]); + PCI_INT(0, 0x3, 0x2, apicid_nb, intr_data_ptr[PIRQ_A]); + PCI_INT(0, 0x3, 0x3, apicid_nb, intr_data_ptr[PIRQ_A]); + PCI_INT(0, 0x3, 0x4, apicid_nb, intr_data_ptr[PIRQ_A]); + PCI_INT(0, 0x3, 0x5, apicid_nb, intr_data_ptr[PIRQ_A]); + + /* PCI slots */ + PCI_INT(0, 0x14, 0x4, apicid_sb, intr_data_ptr[PIRQ_A]); + + /* FCH GPP PCIe Bridges */ + PCI_INT(0x0, 0x15, 0x0, apicid_sb, intr_data_ptr[PIRQ_A]); + /* FCH PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, apicid_sb, intr_data_ptr[PIRQ_A]); + /* FCH PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, apicid_sb, intr_data_ptr[PIRQ_A]); + /* FCH PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, apicid_sb, intr_data_ptr[PIRQ_A]); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + + IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); + + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c new file mode 100644 index 0000000..04d7d9c --- /dev/null +++ b/src/mainboard/amd/lamar/romstage.c @@ -0,0 +1,138 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/stages.h> +#include <device/pnp_def.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include <console/console.h> +#include <console/loglevel.h> +#include <cpu/amd/car.h> +#include <northbridge/amd/pi/agesawrapper.h> +#include <northbridge/amd/pi/agesawrapper_call.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <southbridge/amd/pi/hudson/hudson.h> +#include <cpu/amd/pi/s3_resume.h> +#include "src/drivers/pc80/i8254.c" +#include "src/drivers/pc80/i8259.c" +#include "cbmem.h" +#include "superio/fintek/f81216h/f81216h.h" + +#define SERIAL_DEV PNP_DEV(0x4e, F81216H_SP1) + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; + AGESA_STATUS status = AGESA_UNSUPPORTED; + + /* + * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". This following register setting has been + * replicated in every reference design since Parmer, so it is + * believed to be required even though it is not documented in + * the SoC BKDGs. Without this setting, there is no serial + * output. + */ + outb(0xD2, 0xcd6); + outb(0x00, 0xcd7); + + /* + * The following should be a call to AGESAWRAPPER() macro, but + * that would use console output before it is initialized. + */ + status = agesawrapper_amdinitmmio(); + if (AGESA_SUCCESS != status) { + printk(BIOS_WARNING, "AmdInitMmio reported %s\n", decodeAGESA_STATUS(status)); + } + + outb(0x24, 0xCD6); + outb(0x01, 0xCD7); + *(volatile u32 *) (0xFED80000 + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */ + *(volatile u32 *) (0xFED80000 + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */ + hudson_lpc_port80(); + + if (!cpu_init_detectedx) { + post_code(0x30); + f81216h_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE, MODE_7777); + post_code(0x31); + console_init(); + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + /* Load MPB */ + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + + post_code(0x37); + AGESAWRAPPER(amdinitreset); + post_code(0x38); + printk(BIOS_DEBUG, "Got past hudson_early_setup\n"); + + post_code(0x39); + AGESAWRAPPER(amdinitearly); + int s3resume = acpi_is_wakeup_s3(); + if (!s3resume) { + post_code(0x40); + AGESAWRAPPER(amdinitpost); + + post_code(0x41); + AGESAWRAPPER(amdinitenv); + /* + If code hangs here, please check cahaltasm.S + */ + disable_cache_as_ram(); + } +#if CONFIG_HAVE_ACPI_RESUME + else { /* S3 detect */ + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + AGESAWRAPPER(amdinitresume); + + AGESAWRAPPER(amds3laterestore); + + post_code(0x61); + prepare_for_resume(); + } +#endif + + /* Initialize i8259 pic */ + post_code(0x41); + setup_i8259 (); + + /* Initialize i8254 timers */ + post_code(0x42); + setup_i8254 (); + + post_code(0x50); + copy_and_run(); + + post_code(0x54); /* Should never see this post code. */ +}
-
Dave Frodin