Change in coreboot[master]: cpu/intel/model_6?x{slot_1}: Leave enabling CONFIG_SMP to the mainboard

[Keith Hui (Code Review)]

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37627 )

Change subject: cpu/intel/model_6?x{slot_1}: Leave enabling CONFIG_SMP to the mainboard
......................................................................

cpu/intel/model_6?x{slot_1}: Leave enabling CONFIG_SMP to the mainboard

These predate hyperthreading so they do not SMP unless installed
in a SMP board. Turning SMP off shaves 128 compressed bytes from
ramstage.

Change-Id: I114bdc83ed40ccd9d3996aabf77422236d9d12fa
Signed-off-by: Keith Hui 
---
M src/cpu/intel/model_65x/Kconfig
M src/cpu/intel/model_67x/Kconfig
M src/cpu/intel/model_68x/Kconfig
M src/cpu/intel/model_6bx/Kconfig
M src/cpu/intel/model_6xx/Kconfig
5 files changed, 0 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/37627/1

diff --git a/src/cpu/intel/model_65x/Kconfig b/src/cpu/intel/model_65x/Kconfig
index 4af7145..6a1d09c 100644
--- a/src/cpu/intel/model_65x/Kconfig
+++ b/src/cpu/intel/model_65x/Kconfig
@@ -4,5 +4,4 @@
    select ARCH_VERSTAGE_X86_32
    select ARCH_ROMSTAGE_X86_32
    select ARCH_RAMSTAGE_X86_32
-	select SMP
    select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_67x/Kconfig b/src/cpu/intel/model_67x/Kconfig
index 2da200e..283927f 100644
--- a/src/cpu/intel/model_67x/Kconfig
+++ b/src/cpu/intel/model_67x/Kconfig
@@ -4,5 +4,4 @@
    select ARCH_VERSTAGE_X86_32
    select ARCH_ROMSTAGE_X86_32
    select ARCH_RAMSTAGE_X86_32
-	select SMP
    select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_68x/Kconfig b/src/cpu/intel/model_68x/Kconfig
index 9cca8f8..48888ba 100644
--- a/src/cpu/intel/model_68x/Kconfig
+++ b/src/cpu/intel/model_68x/Kconfig
@@ -18,5 +18,4 @@
    select ARCH_VERSTAGE_X86_32
    select ARCH_ROMSTAGE_X86_32
    select ARCH_RAMSTAGE_X86_32
-	select SMP
    select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_6bx/Kconfig b/src/cpu/intel/model_6bx/Kconfig
index 64f193a..eb4b675 100644
--- a/src/cpu/intel/model_6bx/Kconfig
+++ b/src/cpu/intel/model_6bx/Kconfig
@@ -4,5 +4,4 @@
    select ARCH_VERSTAGE_X86_32
    select ARCH_ROMSTAGE_X86_32
    select ARCH_RAMSTAGE_X86_32
-	select SMP
    select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_6xx/Kconfig b/src/cpu/intel/model_6xx/Kconfig
index 7cafb81..d00fc24 100644
--- a/src/cpu/intel/model_6xx/Kconfig
+++ b/src/cpu/intel/model_6xx/Kconfig
@@ -4,5 +4,4 @@
    select ARCH_VERSTAGE_X86_32
    select ARCH_ROMSTAGE_X86_32
    select ARCH_RAMSTAGE_X86_32
-	select SMP
    select SUPPORT_CPU_UCODE_IN_CBFS

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37627 )

Change subject: cpu/intel/model_6?x{slot_1}: Leave enabling CONFIG_SMP to the mainboard
......................................................................

Patch Set 1: Code-Review+2

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37627 )

Change subject: cpu/intel/model_6?x{slot_1}: Leave enabling CONFIG_SMP to the mainboard
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/37627/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/37627/1//COMMIT_MSG@9 
PS1, Line 9: do not SMP
do not have?

[Idwer Vollering (Code Review)]

Idwer Vollering has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37627 )

Change subject: cpu/intel/model_6?x{slot_1}: Leave enabling CONFIG_SMP to the mainboard
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/37627/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/37627/1//COMMIT_MSG@9 
PS1, Line 9: do not SMP
> do not have?

What is meant here is about the verb '(to) process' in SMP.

[Keith Hui (Code Review)]

Keith Hui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37627 )

Change subject: cpu/intel/model_6?x{slot_1}: Leave enabling CONFIG_SMP to the mainboard
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/37627/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/37627/1//COMMIT_MSG@9 
PS1, Line 9: do not SMP
> do not have?

Do not do

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37627 )

Change subject: cpu/intel/model_6?x{slot_1}: Leave enabling CONFIG_SMP to the mainboard
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/37627/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/37627/1//COMMIT_MSG@9 
PS1, Line 9: do not SMP
> Do not do

Can you please update the commit message accordingly?

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37627 )

Change subject: cpu/intel/model_6?x{slot_1}: Leave enabling CONFIG_SMP to the mainboard
......................................................................

Patch Set 1: Code-Review+2

[Keith Hui (Code Review)]

Hello Kyösti Mälkki, Patrick Rudolph, Angel Pons, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37627

to look at the new patch set (#2).

Change subject: cpu/intel/model_6?x{slot_1}: Leave enabling CONFIG_SMP to the mainboard
......................................................................

cpu/intel/model_6?x{slot_1}: Leave enabling CONFIG_SMP to the mainboard

These predate hyperthreading so they are not SMP capable unless installed
in a SMP board. Turning SMP off shaves 128 compressed bytes from
ramstage.

Change-Id: I114bdc83ed40ccd9d3996aabf77422236d9d12fa
Signed-off-by: Keith Hui 
---
M src/cpu/intel/model_65x/Kconfig
M src/cpu/intel/model_67x/Kconfig
M src/cpu/intel/model_68x/Kconfig
M src/cpu/intel/model_6bx/Kconfig
M src/cpu/intel/model_6xx/Kconfig
5 files changed, 0 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/37627/2

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37627 )

Change subject: cpu/intel/model_6?x{slot_1}: Leave enabling CONFIG_SMP to the mainboard
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/37627/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/37627/1//COMMIT_MSG@9 
PS1, Line 9: do not SMP
> Can you please update the commit message accordingly?

Done

[Nico Huber (Code Review)]

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37627 )

Change subject: cpu/intel/model_6?x{slot_1}: Leave enabling CONFIG_SMP to the mainboard
......................................................................

cpu/intel/model_6?x{slot_1}: Leave enabling CONFIG_SMP to the mainboard

These predate hyperthreading so they are not SMP capable unless installed
in a SMP board. Turning SMP off shaves 128 compressed bytes from
ramstage.

Change-Id: I114bdc83ed40ccd9d3996aabf77422236d9d12fa
Signed-off-by: Keith Hui 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37627
Tested-by: build bot (Jenkins) 
Reviewed-by: Kyösti Mälkki 
Reviewed-by: Angel Pons 
---
M src/cpu/intel/model_65x/Kconfig
M src/cpu/intel/model_67x/Kconfig
M src/cpu/intel/model_68x/Kconfig
M src/cpu/intel/model_6bx/Kconfig
M src/cpu/intel/model_6xx/Kconfig
5 files changed, 0 insertions(+), 5 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Kyösti Mälkki: Looks good to me, approved
  Angel Pons: Looks good to me, approved

diff --git a/src/cpu/intel/model_65x/Kconfig b/src/cpu/intel/model_65x/Kconfig
index 4af7145..6a1d09c 100644
--- a/src/cpu/intel/model_65x/Kconfig
+++ b/src/cpu/intel/model_65x/Kconfig
@@ -4,5 +4,4 @@
    select ARCH_VERSTAGE_X86_32
    select ARCH_ROMSTAGE_X86_32
    select ARCH_RAMSTAGE_X86_32
-	select SMP
    select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_67x/Kconfig b/src/cpu/intel/model_67x/Kconfig
index 2da200e..283927f 100644
--- a/src/cpu/intel/model_67x/Kconfig
+++ b/src/cpu/intel/model_67x/Kconfig
@@ -4,5 +4,4 @@
    select ARCH_VERSTAGE_X86_32
    select ARCH_ROMSTAGE_X86_32
    select ARCH_RAMSTAGE_X86_32
-	select SMP
    select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_68x/Kconfig b/src/cpu/intel/model_68x/Kconfig
index 9cca8f8..48888ba 100644
--- a/src/cpu/intel/model_68x/Kconfig
+++ b/src/cpu/intel/model_68x/Kconfig
@@ -18,5 +18,4 @@
    select ARCH_VERSTAGE_X86_32
    select ARCH_ROMSTAGE_X86_32
    select ARCH_RAMSTAGE_X86_32
-	select SMP
    select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_6bx/Kconfig b/src/cpu/intel/model_6bx/Kconfig
index 64f193a..eb4b675 100644
--- a/src/cpu/intel/model_6bx/Kconfig
+++ b/src/cpu/intel/model_6bx/Kconfig
@@ -4,5 +4,4 @@
    select ARCH_VERSTAGE_X86_32
    select ARCH_ROMSTAGE_X86_32
    select ARCH_RAMSTAGE_X86_32
-	select SMP
    select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_6xx/Kconfig b/src/cpu/intel/model_6xx/Kconfig
index 7cafb81..d00fc24 100644
--- a/src/cpu/intel/model_6xx/Kconfig
+++ b/src/cpu/intel/model_6xx/Kconfig
@@ -4,5 +4,4 @@
    select ARCH_VERSTAGE_X86_32
    select ARCH_ROMSTAGE_X86_32
    select ARCH_RAMSTAGE_X86_32
-	select SMP
    select SUPPORT_CPU_UCODE_IN_CBFS

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37627 )

Change subject: cpu/intel/model_6?x{slot_1}: Leave enabling CONFIG_SMP to the mainboard
......................................................................

Patch Set 3:

Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3
Emulation targets:
EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/162
EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/161
EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/160

Please note: This test is under development and might not be accurate at all!