[XS] Change in coreboot[main]: mb/google/rauru: Add EC suspend pin initial setting

[Yidi Lin (Code Review)]

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu.

Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86381?usp=email )

Change subject: mb/google/rauru: Add EC suspend pin initial setting
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Patch Set 3:

(3 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/86381/comment/a4b0e423_6a014320?usp... :
PS3, Line 7: mb/google/rauru: Add EC suspend pin initial setting
           : 
           : Set the EC suspend pin to output high.
> Just recalled that AP_IN_SLEEP_L is the new sleep source for Rauru, which is decoupled from SRCLKENA […]

mb/google/rarur: Configure AP_IN_SLEEP_L pin

Set AP_IN_SLEEP_L to GPIO mode and output high to notify EC about AP power state.

File src/mainboard/google/rauru/chromeos.c:

https://review.coreboot.org/c/coreboot/+/86381/comment/1e9079bc_04d86ff0?usp... :
PS3, Line 22: 	gpio_output(GPIO_EC_SUSPEND_PIN, 1);
> In ATF plat/mediatek/drivers/spm/mt8196/mt_spm_suspend. […]

EC_SUSPEND_BK_PIN is SPI CS pin. It was a workaround for AP S0/S3 indication for previous manufacturing phase. We don't need to configure it in coreboot.

File src/mainboard/google/rauru/gpio.h:

https://review.coreboot.org/c/coreboot/+/86381/comment/59f2cfc6_d4c1ff6f?usp... :
PS3, Line 8: _OD
> Not related to this patch, but what's `_OD`? The name on the schematics is `BEEP_ON`. […]

@[e-mail] Please help.