Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31048
Change subject: mb/google/octopus: Override emmc DLL values for Ampton ......................................................................
mb/google/octopus: Override emmc DLL values for Ampton
New emmc DLL values for Ampton
BUG=b:122307153 TEST=Boot to OS on 5 systems
Change-Id: Iadd58d254f4bb384f483c2c3e5615f7569d5211c Signed-off-by: Kane Chen kane.chen@intel.com --- M src/mainboard/google/octopus/variants/ampton/overridetree.cb 1 file changed, 41 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/31048/1
diff --git a/src/mainboard/google/octopus/variants/ampton/overridetree.cb b/src/mainboard/google/octopus/variants/ampton/overridetree.cb index 1b4b9ba..10ff7d7 100644 --- a/src/mainboard/google/octopus/variants/ampton/overridetree.cb +++ b/src/mainboard/google/octopus/variants/ampton/overridetree.cb @@ -1,5 +1,46 @@ chip soc/intel/apollolake
+ # EMMC Tx CMD Delay + # Refer to EDS-Vol2-16.32. + # [14:8] steps of delay for DDR mode, each 125ps. + # [6:0] steps of delay for SDR mode, each 125ps. + register "emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-16.33. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0a0c" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-16.34. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x1c292929" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-16.35. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x001a1c1c" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-16.37. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10026" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-16.36. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps. + register "emmc_rx_strobe_cntl" = "0x0a0a" + register "common_soc_config" = "{ .gspi[0] = { .speed_mhz = 1,
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31048 )
Change subject: mb/google/octopus: Override emmc DLL values for Ampton ......................................................................
Patch Set 1: Code-Review+2
Justin TerAvest has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31048 )
Change subject: mb/google/octopus: Override emmc DLL values for Ampton ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31048 )
Change subject: mb/google/octopus: Override emmc DLL values for Ampton ......................................................................
mb/google/octopus: Override emmc DLL values for Ampton
New emmc DLL values for Ampton
BUG=b:122307153 TEST=Boot to OS on 5 systems
Change-Id: Iadd58d254f4bb384f483c2c3e5615f7569d5211c Signed-off-by: Kane Chen kane.chen@intel.com Reviewed-on: https://review.coreboot.org/c/31048 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Justin TerAvest teravest@chromium.org --- M src/mainboard/google/octopus/variants/ampton/overridetree.cb 1 file changed, 41 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Justin TerAvest: Looks good to me, approved
diff --git a/src/mainboard/google/octopus/variants/ampton/overridetree.cb b/src/mainboard/google/octopus/variants/ampton/overridetree.cb index 1b4b9ba..10ff7d7 100644 --- a/src/mainboard/google/octopus/variants/ampton/overridetree.cb +++ b/src/mainboard/google/octopus/variants/ampton/overridetree.cb @@ -1,5 +1,46 @@ chip soc/intel/apollolake
+ # EMMC Tx CMD Delay + # Refer to EDS-Vol2-16.32. + # [14:8] steps of delay for DDR mode, each 125ps. + # [6:0] steps of delay for SDR mode, each 125ps. + register "emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-16.33. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0a0c" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-16.34. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x1c292929" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-16.35. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x001a1c1c" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-16.37. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10026" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-16.36. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps. + register "emmc_rx_strobe_cntl" = "0x0a0a" + register "common_soc_config" = "{ .gspi[0] = { .speed_mhz = 1,
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Furquan Shaikh (Code Review) -
Justin TerAvest (Code Review)
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Kane Chen (Code Review)
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Patrick Georgi (Code Review)