Change in coreboot[master]: soc/amd/sabrina: Modify start address of PSP verstage

[Karthik Ramasubramanian (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held.
Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/63732

to look at the new patch set (#2).

Change subject: soc/amd/sabrina: Modify start address of PSP verstage
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soc/amd/sabrina: Modify start address of PSP verstage

PSP verstage can start at address 0 and use 200KB of PSP SRAM for
execution. Modify both the PSP SRAM start address and size for use by
PSP verstage.

BUG=b:220848544
TEST=Build Skyrim BIOS image with PSP verstage enabled.

Signed-off-by: Karthikeyan Ramasubramanian 
Change-Id: I73e13b82faa0f443570a0c839e7699a79bdae024
---
M src/soc/amd/sabrina/include/soc/psp_verstage_addr.h
1 file changed, 5 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/63732/2