Attention is currently required from: Paul Menzel, Aseda Aboagye. Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52030 )
Change subject: mb/google/dedede: add discrete TPM 2.0 configuration ......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
Do you need any changes to devicetree?
I checked the lalala static.c for presence of tpm device (where I added it in overridetree.cb). Likewise, gspi0 is turned off in lalala. I think I have that covered. FWIW, here's the diff:
``` $ diff -up src/mainboard/google/dedede/variants/magolor/overridetree.cb src/mainboard/google/dedede/variants/lalala/overridetree.cb --- src/mainboard/google/dedede/variants/magolor/overridetree.cb 2021-03-23 15:27:16.294009548 -0600 +++ src/mainboard/google/dedede/variants/lalala/overridetree.cb 2021-04-01 13:44:08.848445091 -0600 @@ -7,10 +7,6 @@ chip soc/intel/jasperlake #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | #| I2C0 | Trackpad | #| I2C1 | TBD | #| I2C2 | Touchscreen | @@ -19,10 +15,6 @@ chip soc/intel/jasperlake #| I2C5 | TBD | #+-------------------+---------------------------+ register "common_soc_config" = "{ - .gspi[0] = { - .speed_mhz = 1, - .early_init = 1, - }, .i2c[0] = { .speed = I2C_SPEED_FAST, .speed_config[0] = { @@ -298,7 +290,13 @@ chip soc/intel/jasperlake device i2c 29 on end end end + device pci 1e.2 off end # GSPI 0 device pci 1f.3 on end # Intel HDA + device pci 1f.5 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end # Discrete TPM + end # chip drivers/pc80/tpm + end # PCH SPI device pci 1c.7 on chip drivers/wifi/generic register "wake" = "GPE0_DW2_03" ```