HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36458 )
Change subject: sb/intel/i82801gx: Use CONFIG_HPET_ADDRESS value ......................................................................
sb/intel/i82801gx: Use CONFIG_HPET_ADDRESS value
Change-Id: I15ae5e70ba351e89d5ea9d04dbb1efdfbb372bba Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/southbridge/intel/i82801gx/acpi/lpc.asl 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/36458/1
diff --git a/src/southbridge/intel/i82801gx/acpi/lpc.asl b/src/southbridge/intel/i82801gx/acpi/lpc.asl index 87eab07..793545d 100644 --- a/src/southbridge/intel/i82801gx/acpi/lpc.asl +++ b/src/southbridge/intel/i82801gx/acpi/lpc.asl @@ -79,7 +79,7 @@
Name(BUF0, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0) + Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) })
Method (_STA, 0) // Device Status
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36458
to look at the new patch set (#2).
Change subject: sb/intel/i82801gx: Use CONFIG_HPET_ADDRESS value ......................................................................
sb/intel/i82801gx: Use CONFIG_HPET_ADDRESS value
Change-Id: I15ae5e70ba351e89d5ea9d04dbb1efdfbb372bba Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/southbridge/intel/i82801gx/acpi/lpc.asl 1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/36458/2
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36458 )
Change subject: sb/intel/i82801gx: Use CONFIG_HPET_ADDRESS value ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36458/2/src/southbridge/intel/i8280... File src/southbridge/intel/i82801gx/acpi/lpc.asl:
https://review.coreboot.org/c/coreboot/+/36458/2/src/southbridge/intel/i8280... PS2, Line 105: Or Nit: Add is more appropriate
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36458 )
Change subject: sb/intel/i82801gx: Use CONFIG_HPET_ADDRESS value ......................................................................
Patch Set 2:
(1 comment)
Thank you
https://review.coreboot.org/c/coreboot/+/36458/2/src/southbridge/intel/i8280... File src/southbridge/intel/i82801gx/acpi/lpc.asl:
https://review.coreboot.org/c/coreboot/+/36458/2/src/southbridge/intel/i8280... PS2, Line 105: Or
Nit: Add is more appropriate
Ack
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36458
to look at the new patch set (#3).
Change subject: sb/intel/i82801gx: Use CONFIG_HPET_ADDRESS value ......................................................................
sb/intel/i82801gx: Use CONFIG_HPET_ADDRESS value
Change-Id: I15ae5e70ba351e89d5ea9d04dbb1efdfbb372bba Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/southbridge/intel/i82801gx/acpi/lpc.asl 1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/36458/3
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36458
to look at the new patch set (#5).
Change subject: sb/intel: Use CONFIG_HPET_ADDRESS value ......................................................................
sb/intel: Use CONFIG_HPET_ADDRESS value
Change-Id: I15ae5e70ba351e89d5ea9d04dbb1efdfbb372bba Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/soc/intel/baytrail/acpi/lpc.asl M src/soc/intel/braswell/acpi/lpc.asl M src/soc/intel/broadwell/acpi/lpc.asl M src/soc/intel/fsp_baytrail/acpi/lpc.asl M src/soc/intel/fsp_broadwell_de/acpi/lpc.asl M src/southbridge/intel/bd82x6x/acpi/lpc.asl M src/southbridge/intel/fsp_rangeley/acpi/lpc.asl M src/southbridge/intel/i82801gx/acpi/lpc.asl M src/southbridge/intel/i82801ix/acpi/lpc.asl M src/southbridge/intel/i82801jx/acpi/lpc.asl M src/southbridge/intel/lynxpoint/acpi/lpc.asl 11 files changed, 32 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/36458/5
Hello Patrick Rudolph, Huang Jin, Philipp Deppenwiese, build bot (Jenkins), David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36458
to look at the new patch set (#7).
Change subject: sb/intel: Use defined CONFIG_HPET_ADDRESS ......................................................................
sb/intel: Use defined CONFIG_HPET_ADDRESS
Change-Id: I15ae5e70ba351e89d5ea9d04dbb1efdfbb372bba Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/soc/intel/baytrail/acpi/lpc.asl M src/soc/intel/braswell/acpi/lpc.asl M src/soc/intel/broadwell/acpi/lpc.asl M src/soc/intel/fsp_baytrail/acpi/lpc.asl M src/soc/intel/fsp_broadwell_de/acpi/lpc.asl M src/southbridge/intel/bd82x6x/acpi/lpc.asl M src/southbridge/intel/fsp_rangeley/acpi/lpc.asl M src/southbridge/intel/i82801gx/acpi/lpc.asl M src/southbridge/intel/i82801ix/acpi/lpc.asl M src/southbridge/intel/i82801jx/acpi/lpc.asl M src/southbridge/intel/lynxpoint/acpi/lpc.asl 11 files changed, 32 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/36458/7
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36458 )
Change subject: sb/intel: Use defined CONFIG_HPET_ADDRESS ......................................................................
Patch Set 7: Code-Review+2
Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36458 )
Change subject: sb/intel: Use defined CONFIG_HPET_ADDRESS ......................................................................
sb/intel: Use defined CONFIG_HPET_ADDRESS
Change-Id: I15ae5e70ba351e89d5ea9d04dbb1efdfbb372bba Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/36458 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M src/soc/intel/baytrail/acpi/lpc.asl M src/soc/intel/braswell/acpi/lpc.asl M src/soc/intel/broadwell/acpi/lpc.asl M src/soc/intel/fsp_baytrail/acpi/lpc.asl M src/soc/intel/fsp_broadwell_de/acpi/lpc.asl M src/southbridge/intel/bd82x6x/acpi/lpc.asl M src/southbridge/intel/fsp_rangeley/acpi/lpc.asl M src/southbridge/intel/i82801gx/acpi/lpc.asl M src/southbridge/intel/i82801ix/acpi/lpc.asl M src/southbridge/intel/i82801jx/acpi/lpc.asl M src/southbridge/intel/lynxpoint/acpi/lpc.asl 11 files changed, 32 insertions(+), 32 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/soc/intel/baytrail/acpi/lpc.asl b/src/soc/intel/baytrail/acpi/lpc.asl index 00aac51..7cdf1aa 100644 --- a/src/soc/intel/baytrail/acpi/lpc.asl +++ b/src/soc/intel/baytrail/acpi/lpc.asl @@ -59,7 +59,7 @@
Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400) + Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400) }) }
diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl index 9caa8f1..a8604d6 100644 --- a/src/soc/intel/braswell/acpi/lpc.asl +++ b/src/soc/intel/braswell/acpi/lpc.asl @@ -71,7 +71,7 @@
Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400) + Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400) }) } #endif diff --git a/src/soc/intel/broadwell/acpi/lpc.asl b/src/soc/intel/broadwell/acpi/lpc.asl index 70dd6e5..ca44c5c 100644 --- a/src/soc/intel/broadwell/acpi/lpc.asl +++ b/src/soc/intel/broadwell/acpi/lpc.asl @@ -74,7 +74,7 @@
Name (BUF0, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0) + Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) })
Method (_STA, 0) // Device Status @@ -99,15 +99,15 @@ _SB.PCI0.LPCB.HPET.FED0._BAS, HPT0)
If (Lequal(HPAS, 1)) { - Store(0xfed01000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) }
If (Lequal(HPAS, 2)) { - Store(0xfed02000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) }
If (Lequal(HPAS, 3)) { - Store(0xfed03000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) } }
diff --git a/src/soc/intel/fsp_baytrail/acpi/lpc.asl b/src/soc/intel/fsp_baytrail/acpi/lpc.asl index 00aac51..7cdf1aa 100644 --- a/src/soc/intel/fsp_baytrail/acpi/lpc.asl +++ b/src/soc/intel/fsp_baytrail/acpi/lpc.asl @@ -59,7 +59,7 @@
Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400) + Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400) }) }
diff --git a/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl b/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl index 6a7a2f1..ef1e655 100644 --- a/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl +++ b/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl @@ -44,7 +44,7 @@
Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400) + Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400) }) }
diff --git a/src/southbridge/intel/bd82x6x/acpi/lpc.asl b/src/southbridge/intel/bd82x6x/acpi/lpc.asl index 5204b29..06c9ada 100644 --- a/src/southbridge/intel/bd82x6x/acpi/lpc.asl +++ b/src/southbridge/intel/bd82x6x/acpi/lpc.asl @@ -97,7 +97,7 @@
Name(BUF0, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0) + Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) })
Method (_STA, 0) // Device Status @@ -120,15 +120,15 @@ If (HPTE) { CreateDWordField(BUF0, _SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) If (Lequal(HPAS, 1)) { - Store(0xfed01000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) }
If (Lequal(HPAS, 2)) { - Store(0xfed02000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) }
If (Lequal(HPAS, 3)) { - Store(0xfed03000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) } }
diff --git a/src/southbridge/intel/fsp_rangeley/acpi/lpc.asl b/src/southbridge/intel/fsp_rangeley/acpi/lpc.asl index b53e98f..a896dad 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi/lpc.asl +++ b/src/southbridge/intel/fsp_rangeley/acpi/lpc.asl @@ -97,7 +97,7 @@
Name(BUF0, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0) + Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) })
Method (_STA, 0) // Device Status @@ -120,15 +120,15 @@ If (HPTE) { CreateDWordField(BUF0, _SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) If (Lequal(HPAS, 1)) { - Store(0xfed01000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) }
If (Lequal(HPAS, 2)) { - Store(0xfed02000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) }
If (Lequal(HPAS, 3)) { - Store(0xfed03000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) } }
diff --git a/src/southbridge/intel/i82801gx/acpi/lpc.asl b/src/southbridge/intel/i82801gx/acpi/lpc.asl index 87eab07..d5201b2 100644 --- a/src/southbridge/intel/i82801gx/acpi/lpc.asl +++ b/src/southbridge/intel/i82801gx/acpi/lpc.asl @@ -79,7 +79,7 @@
Name(BUF0, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0) + Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) })
Method (_STA, 0) // Device Status @@ -102,15 +102,15 @@ If (HPTE) { CreateDWordField(BUF0, _SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) If (Lequal(HPAS, 1)) { - Store(0xfed01000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) }
If (Lequal(HPAS, 2)) { - Store(0xfed02000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) }
If (Lequal(HPAS, 3)) { - Store(0xfed03000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) } }
diff --git a/src/southbridge/intel/i82801ix/acpi/lpc.asl b/src/southbridge/intel/i82801ix/acpi/lpc.asl index 9d27b0b..07ce43a 100644 --- a/src/southbridge/intel/i82801ix/acpi/lpc.asl +++ b/src/southbridge/intel/i82801ix/acpi/lpc.asl @@ -79,7 +79,7 @@
Name(BUF0, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0) + Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) })
Method (_STA, 0) // Device Status @@ -102,15 +102,15 @@ If (HPTE) { CreateDWordField(BUF0, _SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) If (Lequal(HPAS, 1)) { - Store(0xfed01000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) }
If (Lequal(HPAS, 2)) { - Store(0xfed02000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) }
If (Lequal(HPAS, 3)) { - Store(0xfed03000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) } }
diff --git a/src/southbridge/intel/i82801jx/acpi/lpc.asl b/src/southbridge/intel/i82801jx/acpi/lpc.asl index 1d9e54e..7f16e08 100644 --- a/src/southbridge/intel/i82801jx/acpi/lpc.asl +++ b/src/southbridge/intel/i82801jx/acpi/lpc.asl @@ -79,7 +79,7 @@
Name(BUF0, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0) + Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) })
Method (_STA, 0) // Device Status @@ -102,15 +102,15 @@ If (HPTE) { CreateDWordField(BUF0, _SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) If (Lequal(HPAS, 1)) { - Store(0xfed01000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) }
If (Lequal(HPAS, 2)) { - Store(0xfed02000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) }
If (Lequal(HPAS, 3)) { - Store(0xfed03000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) } }
diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl index b677e6a..ddd5a2f 100644 --- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl +++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl @@ -83,7 +83,7 @@
Name(BUF0, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0) + Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) })
Method (_STA, 0) // Device Status @@ -106,15 +106,15 @@ If (HPTE) { CreateDWordField(BUF0, _SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) If (Lequal(HPAS, 1)) { - Store(0xfed01000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) }
If (Lequal(HPAS, 2)) { - Store(0xfed02000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) }
If (Lequal(HPAS, 3)) { - Store(0xfed03000, HPT0) + Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) } }