Change in coreboot[master]: soc/intel/cannonlake: Define Max PCIE Root Ports

[Pratikkumar V Prajapati (Code Review)]

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21272

Change subject: soc/intel/cannonlake: Define Max PCIE Root Ports
......................................................................

soc/intel/cannonlake: Define Max PCIE Root Ports

This patch defines Max PCIE Root Ports and fixes
bellow Coverity scan defect,

*** CID 1380036:  Control flow issues  (NO_EFFECT)
/src/soc/intel/cannonlake/romstage/romstage.c: 80 in soc_memory_init_params()
79
> > > CID 1380036:  Control flow issues  (NO_EFFECT)
> > > "i" is converted to an unsigned type because it's compared to an unsigned constant.

80      for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
81              if (config->PcieRpEnable[i])
82                      mask |= (1 << i);

Change-Id: Id45ff6e96043ed71117018a4e73d08920ae9667e
Signed-off-by: Pratik Prajapati 
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/romstage/romstage.c
2 files changed, 5 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/21272/1

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 65b581e..cf0a534 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -89,6 +89,10 @@
    hex
    default 0x400000

+config MAX_ROOT_PORTS
+	int
+	default 24
+
 config SMM_TSEG_SIZE
    hex
    default 0x800000
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 17c3191..74a2abc 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -68,7 +68,7 @@

static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
 {
-	int i;
+	uint8_t i;
    uint32_t mask = 0;

m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;