Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34996 )
Change subject: AGESA,binaryPI: Fix use of chip.h ......................................................................
AGESA,binaryPI: Fix use of chip.h
Change-Id: I123db3a51a8f354359e8ed5040d23111ea4eb8a4 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/southbridge/amd/agesa/hudson/hudson.h M src/southbridge/amd/agesa/hudson/sd.c M src/southbridge/amd/pi/hudson/hudson.h M src/southbridge/amd/pi/hudson/sd.c 4 files changed, 14 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/34996/1
diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index bd49e8f..5d9d849 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -18,7 +18,6 @@ #define HUDSON_H
#include <device/device.h> -#include "chip.h"
/* Power management index/data registers */ #define BIOSRAM_INDEX 0xcd4 diff --git a/src/southbridge/amd/agesa/hudson/sd.c b/src/southbridge/amd/agesa/hudson/sd.c index cc9470e..25acf0c 100644 --- a/src/southbridge/amd/agesa/hudson/sd.c +++ b/src/southbridge/amd/agesa/hudson/sd.c @@ -18,18 +18,19 @@ #include <device/pci_ids.h> #include <device/pci_ops.h>
+#include "chip.h" #include "hudson.h"
static void sd_init(struct device *dev) { - u32 stepping; + struct southbridge_amd_agesa_hudson_config *sd_chip = dev->chip_info; + u32 stepping = pci_read_config32(pcidev_on_root(0x18, 3), 0xFC); + u8 sd_mode = 0;
- stepping = pci_read_config32(pcidev_on_root(0x18, 3), 0xFC); + if (sd_chip) + sd_mode = sd_chip->sd_mode;
- struct southbridge_amd_agesa_hudson_config *sd_chip = - (struct southbridge_amd_agesa_hudson_config *)(dev->chip_info); - - if (sd_chip->sd_mode == 3) { /* SD 3.0 mode */ + if (sd_mode == 3) { /* SD 3.0 mode */ pci_write_config32(dev, 0xA4, 0x31FEC8B2); pci_write_config32(dev, 0xA8, 0x00002503); pci_write_config32(dev, 0xB0, 0x02180C19); diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index 6afcc65..99e3721 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -19,7 +19,6 @@
#include <types.h> #include <device/device.h> -#include "chip.h"
/* Offsets from ACPI_MMIO_BASE * This is defined by AGESA, but we don't include AGESA headers to avoid diff --git a/src/southbridge/amd/pi/hudson/sd.c b/src/southbridge/amd/pi/hudson/sd.c index e4ace38..c22b988 100644 --- a/src/southbridge/amd/pi/hudson/sd.c +++ b/src/southbridge/amd/pi/hudson/sd.c @@ -18,18 +18,19 @@ #include <device/pci_ids.h> #include <device/pci_ops.h>
+#include "chip.h" #include "hudson.h"
static void sd_init(struct device *dev) { - u32 stepping; + struct southbridge_amd_pi_hudson_config *sd_chip = dev->chip_info; + u32 stepping = pci_read_config32(pcidev_on_root(0x18, 3), 0xFC); + u8 sd_mode = 0;
- stepping = pci_read_config32(pcidev_on_root(0x18, 3), 0xFC); + if (sd_chip) + sd_mode = sd_chip->sd_mode;
- struct southbridge_amd_pi_hudson_config *sd_chip = - (struct southbridge_amd_pi_hudson_config *)(dev->chip_info); - - if (sd_chip->sd_mode == 3) { /* SD 3.0 mode */ + if (sd_mode == 3) { /* SD 3.0 mode */ pci_write_config32(dev, 0xA4, 0x31FEC8B2); pci_write_config32(dev, 0xA8, 0x00002503); pci_write_config32(dev, 0xB0, 0x02180C19);
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34996 )
Change subject: AGESA,binaryPI: Fix use of chip.h ......................................................................
Patch Set 1: Code-Review+2
Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34996 )
Change subject: AGESA,binaryPI: Fix use of chip.h ......................................................................
AGESA,binaryPI: Fix use of chip.h
Change-Id: I123db3a51a8f354359e8ed5040d23111ea4eb8a4 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34996 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Marshall Dawson marshalldawson3rd@gmail.com --- M src/southbridge/amd/agesa/hudson/hudson.h M src/southbridge/amd/agesa/hudson/sd.c M src/southbridge/amd/pi/hudson/hudson.h M src/southbridge/amd/pi/hudson/sd.c 4 files changed, 14 insertions(+), 14 deletions(-)
Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved
diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index bd49e8f..5d9d849 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -18,7 +18,6 @@ #define HUDSON_H
#include <device/device.h> -#include "chip.h"
/* Power management index/data registers */ #define BIOSRAM_INDEX 0xcd4 diff --git a/src/southbridge/amd/agesa/hudson/sd.c b/src/southbridge/amd/agesa/hudson/sd.c index cc9470e..25acf0c 100644 --- a/src/southbridge/amd/agesa/hudson/sd.c +++ b/src/southbridge/amd/agesa/hudson/sd.c @@ -18,18 +18,19 @@ #include <device/pci_ids.h> #include <device/pci_ops.h>
+#include "chip.h" #include "hudson.h"
static void sd_init(struct device *dev) { - u32 stepping; + struct southbridge_amd_agesa_hudson_config *sd_chip = dev->chip_info; + u32 stepping = pci_read_config32(pcidev_on_root(0x18, 3), 0xFC); + u8 sd_mode = 0;
- stepping = pci_read_config32(pcidev_on_root(0x18, 3), 0xFC); + if (sd_chip) + sd_mode = sd_chip->sd_mode;
- struct southbridge_amd_agesa_hudson_config *sd_chip = - (struct southbridge_amd_agesa_hudson_config *)(dev->chip_info); - - if (sd_chip->sd_mode == 3) { /* SD 3.0 mode */ + if (sd_mode == 3) { /* SD 3.0 mode */ pci_write_config32(dev, 0xA4, 0x31FEC8B2); pci_write_config32(dev, 0xA8, 0x00002503); pci_write_config32(dev, 0xB0, 0x02180C19); diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index 6afcc65..99e3721 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -19,7 +19,6 @@
#include <types.h> #include <device/device.h> -#include "chip.h"
/* Offsets from ACPI_MMIO_BASE * This is defined by AGESA, but we don't include AGESA headers to avoid diff --git a/src/southbridge/amd/pi/hudson/sd.c b/src/southbridge/amd/pi/hudson/sd.c index e4ace38..c22b988 100644 --- a/src/southbridge/amd/pi/hudson/sd.c +++ b/src/southbridge/amd/pi/hudson/sd.c @@ -18,18 +18,19 @@ #include <device/pci_ids.h> #include <device/pci_ops.h>
+#include "chip.h" #include "hudson.h"
static void sd_init(struct device *dev) { - u32 stepping; + struct southbridge_amd_pi_hudson_config *sd_chip = dev->chip_info; + u32 stepping = pci_read_config32(pcidev_on_root(0x18, 3), 0xFC); + u8 sd_mode = 0;
- stepping = pci_read_config32(pcidev_on_root(0x18, 3), 0xFC); + if (sd_chip) + sd_mode = sd_chip->sd_mode;
- struct southbridge_amd_pi_hudson_config *sd_chip = - (struct southbridge_amd_pi_hudson_config *)(dev->chip_info); - - if (sd_chip->sd_mode == 3) { /* SD 3.0 mode */ + if (sd_mode == 3) { /* SD 3.0 mode */ pci_write_config32(dev, 0xA4, 0x31FEC8B2); pci_write_config32(dev, 0xA8, 0x00002503); pci_write_config32(dev, 0xB0, 0x02180C19);
-
Kyösti Mälkki (Code Review) -
Marshall Dawson (Code Review)