Change in coreboot[master]: nb/intel/sandybridge: Use bitfield for GDCRTRAININGMOD register
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47572 )
Change subject: nb/intel/sandybridge: Use bitfield for GDCRTRAININGMOD register ......................................................................
nb/intel/sandybridge: Use bitfield for GDCRTRAININGMOD register
Change-Id: Ie4b5777dd3789d4cd818ee66bdf3074ad055c818 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h 2 files changed, 55 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/47572/1
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 4b28eff..f20181e 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1324,7 +1324,12 @@ /* Execute command queue */ iosav_run_once(channel);
- MCHBAR32(GDCRTRAININGMOD) = (slotrank << 2) | 0x8001; + const union gdcr_training_mod_reg training_mod = { + .receive_enable_mode = 1, + .training_rank_sel = slotrank, + .odt_always_on = 1, + }; + MCHBAR32(GDCRTRAININGMOD) = training_mod.raw;
ctrl->timings[channel][slotrank].io_latency = 4; ctrl->timings[channel][slotrank].roundtrip_latency = 55; @@ -1754,7 +1759,14 @@ int statistics[NUM_LANES][128]; int lane;
- MCHBAR32(GDCRTRAININGMOD) = 0x108052 | (slotrank << 2); + const union gdcr_training_mod_reg training_mod = { + .write_leveling_mode = 1, + .training_rank_sel = slotrank, + .enable_dqs_wl = 5, + .odt_always_on = 1, + .force_drive_enable = 1, + }; + MCHBAR32(GDCRTRAININGMOD) = training_mod.raw;
for (timB = 0; timB < 128; timB++) { FOR_ALL_LANES { @@ -1824,7 +1836,12 @@ static void train_write_flyby(ramctr_timing *ctrl) { int channel, slotrank, lane, old; - MCHBAR32(GDCRTRAININGMOD) = 0x200; + + const union gdcr_training_mod_reg training_mod = { + .dq_dqs_training_res = 1, + }; + MCHBAR32(GDCRTRAININGMOD) = training_mod.raw; + FOR_ALL_POPULATED_CHANNELS { fill_pattern1(ctrl, channel); } @@ -1983,7 +2000,13 @@ write_mrreg(ctrl, channel, slotrank, 1, make_mr1(ctrl, slotrank, channel) | 1 << 12 | 1 << 7);
- MCHBAR32(GDCRTRAININGMOD) = 0x108052; + const union gdcr_training_mod_reg training_mod = { + .write_leveling_mode = 1, + .enable_dqs_wl = 5, + .odt_always_on = 1, + .force_drive_enable = 1, + }; + MCHBAR32(GDCRTRAININGMOD) = training_mod.raw;
toggle_io_reset();
@@ -2483,8 +2506,11 @@ }
for (i = 0; i < 3; i++) { - MCHBAR32(GDCRTRAININGMOD_ch(channel)) = reg3000b24[i] << 24; - printram("[%x] = 0x%08x\n", GDCRTRAININGMOD_ch(channel), reg3000b24[i] << 24); + const union gdcr_training_mod_reg training_mod = { + .vref_gen_ctl = reg3000b24[i], + }; + MCHBAR32(GDCRTRAININGMOD_ch(channel)) = training_mod.raw; + printram("[%x] = 0x%08x\n", GDCRTRAININGMOD_ch(channel), training_mod.raw);
for (pat = 0; pat < NUM_PATTERNS; pat++) { fill_pattern5(ctrl, channel, pat); diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 2244048..de74af5 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -117,6 +117,29 @@ u32 raw; };
+union gdcr_training_mod_reg { + struct { + u32 receive_enable_mode : 1; /* [ 0.. 0] */ + u32 write_leveling_mode : 1; /* [ 1.. 1] */ + u32 training_rank_sel : 2; /* [ 3.. 2] */ + u32 enable_dqs_wl : 4; /* [ 7.. 4] */ + u32 dqs_logic_delay_wl : 1; /* [ 8.. 8] */ + u32 dq_dqs_training_res : 1; /* [ 9.. 9] */ + u32 : 4; + u32 delay_dq : 1; /* [14..14] */ + u32 odt_always_on : 1; /* [15..15] */ + u32 : 4; + u32 force_drive_enable : 1; /* [20..20] */ + u32 dft_tx_pi_clk_view : 1; /* [21..21] */ + u32 dft_tx_pi_clk_swap : 4; /* [22..22] */ + u32 early_odt_en : 1; /* [23..23] */ + u32 vref_gen_ctl : 6; /* [29..24] */ + u32 ext_vref_sel : 1; /* [30..30] */ + u32 tx_fifo_always_on : 1; /* [31..31] */ + }; + u32 raw; +}; + union tc_dbp_reg { struct { u32 tRCD : 4; /* [ 3.. 0] */
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47572 )
Change subject: nb/intel/sandybridge: Use bitfield for GDCRTRAININGMOD register ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/47572/1/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.h:
https://review.coreboot.org/c/coreboot/+/47572/1/src/northbridge/intel/sandy... PS1, Line 128: u32 : 4; space prohibited before that ':' (ctx:WxW)
https://review.coreboot.org/c/coreboot/+/47572/1/src/northbridge/intel/sandy... PS1, Line 131: u32 : 4; space prohibited before that ':' (ctx:WxW)
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47572
to look at the new patch set (#2).
Change subject: nb/intel/sandybridge: Use bitfield for GDCRTRAININGMOD register ......................................................................
nb/intel/sandybridge: Use bitfield for GDCRTRAININGMOD register
Tested on Asus P8H61-M PRO, still boots.
Change-Id: Ie4b5777dd3789d4cd818ee66bdf3074ad055c818 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h 2 files changed, 55 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/47572/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47572 )
Change subject: nb/intel/sandybridge: Use bitfield for GDCRTRAININGMOD register ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/47572/2/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.h:
https://review.coreboot.org/c/coreboot/+/47572/2/src/northbridge/intel/sandy... PS2, Line 128: u32 : 4; space prohibited before that ':' (ctx:WxW)
https://review.coreboot.org/c/coreboot/+/47572/2/src/northbridge/intel/sandy... PS2, Line 131: u32 : 4; space prohibited before that ':' (ctx:WxW)
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47572 )
Change subject: nb/intel/sandybridge: Use bitfield for GDCRTRAININGMOD register ......................................................................
Patch Set 2: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47572 )
Change subject: nb/intel/sandybridge: Use bitfield for GDCRTRAININGMOD register ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47572/2/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.c:
https://review.coreboot.org/c/coreboot/+/47572/2/src/northbridge/intel/sandy... PS2, Line 2510: .vref_gen_ctl = reg3000b24[i], This seems to not work well anymore...
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47572 )
Change subject: nb/intel/sandybridge: Use bitfield for GDCRTRAININGMOD register ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47572/2/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.h:
https://review.coreboot.org/c/coreboot/+/47572/2/src/northbridge/intel/sandy... PS2, Line 134: 4 you doofus
Hello build bot (Jenkins), Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47572
to look at the new patch set (#3).
Change subject: nb/intel/sandybridge: Use bitfield for GDCRTRAININGMOD register ......................................................................
nb/intel/sandybridge: Use bitfield for GDCRTRAININGMOD register
Tested on Asus P8H61-M PRO, still boots.
Change-Id: Ie4b5777dd3789d4cd818ee66bdf3074ad055c818 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h 2 files changed, 55 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/47572/3
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47572 )
Change subject: nb/intel/sandybridge: Use bitfield for GDCRTRAININGMOD register ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/47572/2/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.h:
https://review.coreboot.org/c/coreboot/+/47572/2/src/northbridge/intel/sandy... PS2, Line 134: 4
you doofus
Done
https://review.coreboot.org/c/coreboot/+/47572/2/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.c:
https://review.coreboot.org/c/coreboot/+/47572/2/src/northbridge/intel/sandy... PS2, Line 2510: .vref_gen_ctl = reg3000b24[i],
This seems to not work well anymore...
Done
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47572 )
Change subject: nb/intel/sandybridge: Use bitfield for GDCRTRAININGMOD register ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/47572/3/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.h:
https://review.coreboot.org/c/coreboot/+/47572/3/src/northbridge/intel/sandy... PS3, Line 128: u32 : 4; space prohibited before that ':' (ctx:WxW)
https://review.coreboot.org/c/coreboot/+/47572/3/src/northbridge/intel/sandy... PS3, Line 131: u32 : 4; space prohibited before that ':' (ctx:WxW)
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47572 )
Change subject: nb/intel/sandybridge: Use bitfield for GDCRTRAININGMOD register ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/47572/4/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.h:
https://review.coreboot.org/c/coreboot/+/47572/4/src/northbridge/intel/sandy... PS4, Line 128: u32 : 4; space prohibited before that ':' (ctx:WxW)
https://review.coreboot.org/c/coreboot/+/47572/4/src/northbridge/intel/sandy... PS4, Line 131: u32 : 4; space prohibited before that ':' (ctx:WxW)
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47572 )
Change subject: nb/intel/sandybridge: Use bitfield for GDCRTRAININGMOD register ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/47572/5/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.h:
https://review.coreboot.org/c/coreboot/+/47572/5/src/northbridge/intel/sandy... PS5, Line 128: u32 : 4; space prohibited before that ':' (ctx:WxW)
https://review.coreboot.org/c/coreboot/+/47572/5/src/northbridge/intel/sandy... PS5, Line 131: u32 : 4; space prohibited before that ':' (ctx:WxW)
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47572 )
Change subject: nb/intel/sandybridge: Use bitfield for GDCRTRAININGMOD register ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/47572/6/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.h:
https://review.coreboot.org/c/coreboot/+/47572/6/src/northbridge/intel/sandy... PS6, Line 128: u32 : 4; space prohibited before that ':' (ctx:WxW)
https://review.coreboot.org/c/coreboot/+/47572/6/src/northbridge/intel/sandy... PS6, Line 131: u32 : 4; space prohibited before that ':' (ctx:WxW)
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47572 )
Change subject: nb/intel/sandybridge: Use bitfield for GDCRTRAININGMOD register ......................................................................
Patch Set 6: Code-Review+2
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47572 )
Change subject: nb/intel/sandybridge: Use bitfield for GDCRTRAININGMOD register ......................................................................
nb/intel/sandybridge: Use bitfield for GDCRTRAININGMOD register
Tested on Asus P8H61-M PRO, still boots.
Change-Id: Ie4b5777dd3789d4cd818ee66bdf3074ad055c818 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/47572 Reviewed-by: Arthur Heymans arthur@aheymans.xyz Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h 2 files changed, 55 insertions(+), 6 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 60f9e1f..5aaafdd 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1351,7 +1351,12 @@ /* Execute command queue */ iosav_run_once(channel);
- MCHBAR32(GDCRTRAININGMOD) = (slotrank << 2) | 0x8001; + const union gdcr_training_mod_reg training_mod = { + .receive_enable_mode = 1, + .training_rank_sel = slotrank, + .odt_always_on = 1, + }; + MCHBAR32(GDCRTRAININGMOD) = training_mod.raw;
ctrl->timings[channel][slotrank].io_latency = 4; ctrl->timings[channel][slotrank].roundtrip_latency = 55; @@ -1814,7 +1819,14 @@ int statistics[NUM_LANES][128]; int lane;
- MCHBAR32(GDCRTRAININGMOD) = 0x108052 | (slotrank << 2); + const union gdcr_training_mod_reg training_mod = { + .write_leveling_mode = 1, + .training_rank_sel = slotrank, + .enable_dqs_wl = 5, + .odt_always_on = 1, + .force_drive_enable = 1, + }; + MCHBAR32(GDCRTRAININGMOD) = training_mod.raw;
for (timB = 0; timB < 128; timB++) { FOR_ALL_LANES { @@ -1884,7 +1896,12 @@ static void train_write_flyby(ramctr_timing *ctrl) { int channel, slotrank, lane, old; - MCHBAR32(GDCRTRAININGMOD) = 0x200; + + const union gdcr_training_mod_reg training_mod = { + .dq_dqs_training_res = 1, + }; + MCHBAR32(GDCRTRAININGMOD) = training_mod.raw; + FOR_ALL_POPULATED_CHANNELS { fill_pattern1(ctrl, channel); } @@ -2046,7 +2063,13 @@ write_mrreg(ctrl, channel, slotrank, 1, make_mr1(ctrl, slotrank, channel) | 1 << 12 | 1 << 7);
- MCHBAR32(GDCRTRAININGMOD) = 0x108052; + const union gdcr_training_mod_reg training_mod = { + .write_leveling_mode = 1, + .enable_dqs_wl = 5, + .odt_always_on = 1, + .force_drive_enable = 1, + }; + MCHBAR32(GDCRTRAININGMOD) = training_mod.raw;
toggle_io_reset();
@@ -2522,8 +2545,11 @@ }
for (i = 0; i < 3; i++) { - MCHBAR32(GDCRTRAININGMOD_ch(channel)) = reg3000b24[i] << 24; - printram("[%x] = 0x%08x\n", GDCRTRAININGMOD_ch(channel), reg3000b24[i] << 24); + const union gdcr_training_mod_reg training_mod = { + .vref_gen_ctl = reg3000b24[i], + }; + MCHBAR32(GDCRTRAININGMOD_ch(channel)) = training_mod.raw; + printram("[%x] = 0x%08x\n", GDCRTRAININGMOD_ch(channel), training_mod.raw);
for (pat = 0; pat < NUM_PATTERNS; pat++) { fill_pattern5(ctrl, channel, pat); diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 798b482..4a7e806 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -117,6 +117,29 @@ u32 raw; };
+union gdcr_training_mod_reg { + struct { + u32 receive_enable_mode : 1; /* [ 0.. 0] */ + u32 write_leveling_mode : 1; /* [ 1.. 1] */ + u32 training_rank_sel : 2; /* [ 3.. 2] */ + u32 enable_dqs_wl : 4; /* [ 7.. 4] */ + u32 dqs_logic_delay_wl : 1; /* [ 8.. 8] */ + u32 dq_dqs_training_res : 1; /* [ 9.. 9] */ + u32 : 4; + u32 delay_dq : 1; /* [14..14] */ + u32 odt_always_on : 1; /* [15..15] */ + u32 : 4; + u32 force_drive_enable : 1; /* [20..20] */ + u32 dft_tx_pi_clk_view : 1; /* [21..21] */ + u32 dft_tx_pi_clk_swap : 1; /* [22..22] */ + u32 early_odt_en : 1; /* [23..23] */ + u32 vref_gen_ctl : 6; /* [29..24] */ + u32 ext_vref_sel : 1; /* [30..30] */ + u32 tx_fifo_always_on : 1; /* [31..31] */ + }; + u32 raw; +}; + union tc_dbp_reg { struct { u32 tRCD : 4; /* [ 3.. 0] */
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)
-
build bot (Jenkins) (Code Review)
-
Felix Held (Code Review)