Hello Patrick Rudolph,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/35791
to review the following change.
Change subject: soc/intel/common/block/p2sb/p2sb: Add missing PCI IDs ......................................................................
soc/intel/common/block/p2sb/p2sb: Add missing PCI IDs
The code is compiled on SKL/KBL, but the P2SB PCI IDs were missing. Add them to make sure that the BAR0 doesn't change when running PCI resource allocation.
Change-Id: I7cffbbc7d15dad14cccd122a081099b51dc1ce07 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/include/device/pci_ids.h M src/soc/intel/common/block/p2sb/p2sb.c 2 files changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/35791/1
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 905618c..2bc43da 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3247,6 +3247,9 @@ #define PCI_DEVICE_ID_INTEL_GLK_P2SB 0x3192 #define PCI_DEVICE_ID_INTEL_LWB_P2SB 0xa1a0 #define PCI_DEVICE_ID_INTEL_LWB_P2SB_SUPER 0xa220 +#define PCI_DEVICE_ID_INTEL_SKL_LP_P2SB 0x9d20 +#define PCI_DEVICE_ID_INTEL_SKL_P2SB 0xa120 +#define PCI_DEVICE_ID_INTEL_KBL_P2SB 0xa2a0 #define PCI_DEVICE_ID_INTEL_CNL_P2SB 0x9da0 #define PCI_DEVICE_ID_INTEL_CNP_H_P2SB 0xa320 #define PCI_DEVICE_ID_INTEL_ICL_P2SB 0x34a0 diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 1df0567..14e1fd9 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -155,6 +155,8 @@ /* * There's only one resource on the P2SB device. It's also already * manually set to a fixed address in earlier boot stages. + * The following code makes sure that it doesn't change if the device + * is visible and the resource allocator is being run. */ mmio_resource(dev, PCI_BASE_ADDRESS_0, P2SB_BAR / KiB, P2SB_SIZE / KiB); } @@ -170,6 +172,9 @@ PCI_DEVICE_ID_INTEL_GLK_P2SB, PCI_DEVICE_ID_INTEL_LWB_P2SB, PCI_DEVICE_ID_INTEL_LWB_P2SB_SUPER, + PCI_DEVICE_ID_INTEL_SKL_LP_P2SB, + PCI_DEVICE_ID_INTEL_SKL_P2SB, + PCI_DEVICE_ID_INTEL_KBL_P2SB, PCI_DEVICE_ID_INTEL_CNL_P2SB, PCI_DEVICE_ID_INTEL_CNP_H_P2SB, PCI_DEVICE_ID_INTEL_ICL_P2SB,
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35791 )
Change subject: soc/intel/common/block/p2sb/p2sb: Add missing PCI IDs ......................................................................
Patch Set 1: Code-Review+1
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35791 )
Change subject: soc/intel/common/block/p2sb/p2sb: Add missing PCI IDs ......................................................................
Patch Set 1: Code-Review+2
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35791 )
Change subject: soc/intel/common/block/p2sb/p2sb: Add missing PCI IDs ......................................................................
Patch Set 1: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35791 )
Change subject: soc/intel/common/block/p2sb/p2sb: Add missing PCI IDs ......................................................................
Patch Set 1: Code-Review+2
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35791 )
Change subject: soc/intel/common/block/p2sb/p2sb: Add missing PCI IDs ......................................................................
soc/intel/common/block/p2sb/p2sb: Add missing PCI IDs
The code is compiled on SKL/KBL, but the P2SB PCI IDs were missing. Add them to make sure that the BAR0 doesn't change when running PCI resource allocation.
Change-Id: I7cffbbc7d15dad14cccd122a081099b51dc1ce07 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35791 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Felix Held felix-coreboot@felixheld.de Reviewed-by: Aaron Durbin adurbin@chromium.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/include/device/pci_ids.h M src/soc/intel/common/block/p2sb/p2sb.c 2 files changed, 8 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Aaron Durbin: Looks good to me, approved Felix Held: Looks good to me, approved Furquan Shaikh: Looks good to me, approved
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index b828eaa..6abedb4 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3265,6 +3265,9 @@ #define PCI_DEVICE_ID_INTEL_GLK_P2SB 0x3192 #define PCI_DEVICE_ID_INTEL_LWB_P2SB 0xa1a0 #define PCI_DEVICE_ID_INTEL_LWB_P2SB_SUPER 0xa220 +#define PCI_DEVICE_ID_INTEL_SKL_LP_P2SB 0x9d20 +#define PCI_DEVICE_ID_INTEL_SKL_P2SB 0xa120 +#define PCI_DEVICE_ID_INTEL_KBL_P2SB 0xa2a0 #define PCI_DEVICE_ID_INTEL_CNL_P2SB 0x9da0 #define PCI_DEVICE_ID_INTEL_CNP_H_P2SB 0xa320 #define PCI_DEVICE_ID_INTEL_ICL_P2SB 0x34a0 diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 1df0567..14e1fd9 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -155,6 +155,8 @@ /* * There's only one resource on the P2SB device. It's also already * manually set to a fixed address in earlier boot stages. + * The following code makes sure that it doesn't change if the device + * is visible and the resource allocator is being run. */ mmio_resource(dev, PCI_BASE_ADDRESS_0, P2SB_BAR / KiB, P2SB_SIZE / KiB); } @@ -170,6 +172,9 @@ PCI_DEVICE_ID_INTEL_GLK_P2SB, PCI_DEVICE_ID_INTEL_LWB_P2SB, PCI_DEVICE_ID_INTEL_LWB_P2SB_SUPER, + PCI_DEVICE_ID_INTEL_SKL_LP_P2SB, + PCI_DEVICE_ID_INTEL_SKL_P2SB, + PCI_DEVICE_ID_INTEL_KBL_P2SB, PCI_DEVICE_ID_INTEL_CNL_P2SB, PCI_DEVICE_ID_INTEL_CNP_H_P2SB, PCI_DEVICE_ID_INTEL_ICL_P2SB,
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Aaron Durbin (Code Review) -
Felix Held (Code Review)
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Furquan Shaikh (Code Review)
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Patrick Rudolph (Code Review)
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Paul Menzel (Code Review)