Change in coreboot[master]: soc/intel/broadwell: Include EC and IRQ links ACPI early

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46766 )

Change subject: soc/intel/broadwell: Include EC and IRQ links ACPI early
......................................................................

soc/intel/broadwell: Include EC and IRQ links ACPI early

Other southbridges such as Lynx Point do it. This eases merging later.

Change-Id: I10196bbc44ce859c2747755845378351f45944ae
Signed-off-by: Angel Pons 
---
M src/soc/intel/broadwell/pch/acpi/lpc.asl
1 file changed, 4 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/46766/1

diff --git a/src/soc/intel/broadwell/pch/acpi/lpc.asl b/src/soc/intel/broadwell/pch/acpi/lpc.asl
index 01e1beb..0af85e6 100644
--- a/src/soc/intel/broadwell/pch/acpi/lpc.asl
+++ b/src/soc/intel/broadwell/pch/acpi/lpc.asl
@@ -31,6 +31,10 @@
    	IOD1,	8,
    }

+	#include <southbridge/intel/common/acpi/irqlinks.asl>
+
+	#include "acpi/ec.asl"
+
    Device (DMAC)	// DMA Controller
    {
    	Name (_HID, EISAID("PNP0200"))
@@ -180,7 +184,5 @@
    }

#include "gpio.asl"
-	#include <southbridge/intel/common/acpi/irqlinks.asl>
-	#include "acpi/ec.asl"
    #include "acpi/superio.asl"
 }

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46766 )

Change subject: soc/intel/broadwell: Include EC and IRQ links ACPI early
......................................................................

Patch Set 9: Code-Review+2

[Angel Pons (Code Review)]

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46766 )

Change subject: soc/intel/broadwell: Include EC and IRQ links ACPI early
......................................................................

soc/intel/broadwell: Include EC and IRQ links ACPI early

Other southbridges such as Lynx Point do it. This eases merging later.

Change-Id: I10196bbc44ce859c2747755845378351f45944ae
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46766
Reviewed-by: Michael Niewöhner 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/broadwell/pch/acpi/lpc.asl
1 file changed, 4 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Michael Niewöhner: Looks good to me, approved

diff --git a/src/soc/intel/broadwell/pch/acpi/lpc.asl b/src/soc/intel/broadwell/pch/acpi/lpc.asl
index 01e1beb..0af85e6 100644
--- a/src/soc/intel/broadwell/pch/acpi/lpc.asl
+++ b/src/soc/intel/broadwell/pch/acpi/lpc.asl
@@ -31,6 +31,10 @@
    	IOD1,	8,
    }

+	#include <southbridge/intel/common/acpi/irqlinks.asl>
+
+	#include "acpi/ec.asl"
+
    Device (DMAC)	// DMA Controller
    {
    	Name (_HID, EISAID("PNP0200"))
@@ -180,7 +184,5 @@
    }

#include "gpio.asl"
-	#include <southbridge/intel/common/acpi/irqlinks.asl>
-	#include "acpi/ec.asl"
    #include "acpi/superio.asl"
 }