Change in coreboot[master]: soc/amd/common/block/lpc: use 32 bit accesses in lpc_enable_port80

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson.
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59676 )

Change subject: soc/amd/common/block/lpc: use 32 bit accesses in lpc_enable_port80
......................................................................

soc/amd/common/block/lpc: use 32 bit accesses in lpc_enable_port80

When using 32 bit PCI accesses in lpc_enable_port80, we can use the
LPC_IO_OR_MEM_DECODE_ENABLE and DECODE_IO_PORT_ENABLE4 defines and don't
need to re-define bits with offsets from the beginning of the third byte
within this 32 bit register. This allows to drop the
LPC_IO_OR_MEM_DEC_EN_HIGH register definition which points to
LPC_IO_OR_MEM_DECODE_ENABLE + 2 and to drop the re-definitions of the
bit re-definitions with a different offset.

The code in lpc_enable_port80 was originally copied from sb/amd/agesa/
hudson/early_setup.c which might be sort-of a copy from what the AGESA
reference code does.

TEST=When commenting out SOC_AMD_COMMON_BLOCK_USE_ESPI in the Kconfig of
Mandolin and selecting AMD_LPC_DEBUG_CARD, all POST codes still get
shown on the POST code LED display when this patch is applied.

Signed-off-by: Felix Held 
Change-Id: I001bb1c2ccf99e36d4fbd73d3bf96b78ddb87d67
---
M src/soc/amd/common/block/include/amdblocks/lpc.h
M src/soc/amd/common/block/lpc/lpc_util.c
2 files changed, 4 insertions(+), 16 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/59676/1

diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h
index 44a0c02..173cbd1 100644
--- a/src/soc/amd/common/block/include/amdblocks/lpc.h
+++ b/src/soc/amd/common/block/include/amdblocks/lpc.h
@@ -69,18 +69,6 @@
 #define     LPC_SELECT_SIO_2E2F		0
 #define   WIDEIO_RANGE_ERROR		-1

-/* Assuming word access to higher word (register 0x4a) */
-#define LPC_IO_OR_MEM_DEC_EN_HIGH	0x4a
-#define   LPC_WIDEIO2_ENABLE_H		BIT(9)
-#define   LPC_WIDEIO1_ENABLE_H		BIT(8)
-#define   DECODE_IO_PORT_ENABLE6_H	BIT(7)
-#define   DECODE_IO_PORT_ENABLE5_H	BIT(6)
-#define   DECODE_IO_PORT_ENABLE4_H	BIT(5)
-#define   DECODE_IO_PORT_ENABLE3_H	BIT(3)
-#define   DECODE_IO_PORT_ENABLE2_H	BIT(2)
-#define   DECODE_IO_PORT_ENABLE1_H	BIT(1)
-#define   DECODE_IO_PORT_ENABLE0_H	BIT(0)
-
 #define LPC_MEM_PORT1			0x4c
 #define ROM_PROTECT_RANGE0		0x50
 #define   ROM_BASE_MASK			0xfffff000		/* bits 31-12 */
diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c
index c40a198..7291959 100644
--- a/src/soc/amd/common/block/lpc/lpc_util.c
+++ b/src/soc/amd/common/block/lpc/lpc_util.c
@@ -138,11 +138,11 @@

void lpc_enable_port80(void)
 {
-	u8 byte;
+	uint32_t tmp;

-	byte = pci_read_config8(_LPCB_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH);
-	byte |= DECODE_IO_PORT_ENABLE4_H;
-	pci_write_config8(_LPCB_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte);
+	tmp = pci_read_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE);
+	tmp |= DECODE_IO_PORT_ENABLE4;
+	pci_write_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, tmp);
 }

void lpc_enable_sio_decode(const bool addr)