Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8325
-gerrit
commit 71d20cc3a4d4bb696db341f73553480ae80ecb93 Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Fri Nov 14 16:20:22 2014 +0200
pcengines/apu1: New board PC Engines APU1
While we cannot recreate exact copies of PC Engines APU1 firmware images, I shall upstream the vital changes for coreboot from the following tarballs SAGE has published to meet GPL:
SageBios_PCEngines_APU_sources_for_publishing_20140405_GPL_package.tar.gz md5sum: ce5f54723e4fe3b63a1a3e35586728d4
pcengines.apu_139_osp.tar.gz md5sum: af6c8ab3b85d1a5a9fbeb41efa30a1ef
The patch here adds Kconfig, Makefile.inc and devicetree.cb files to match 2014/04/05 release tarball config.h and static.c files.
Change-Id: Id61270b4d484f712a5c0e780a01fc81f1550b9ad Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/mainboard/pcengines/Kconfig | 3 + src/mainboard/pcengines/apu1/BiosCallOuts.c | 27 ++- .../pcengines/apu1/HYNIX-H5TQ2G83CFR.spd.hex | 251 ++++++++++++++++++++ .../pcengines/apu1/HYNIX-H5TQ4G83MFR.spd.hex | 253 +++++++++++++++++++++ src/mainboard/pcengines/apu1/Kconfig | 16 +- src/mainboard/pcengines/apu1/Makefile.inc | 22 ++ src/mainboard/pcengines/apu1/PlatformGnbPcie.c | 22 +- .../pcengines/apu1/PlatformGnbPcieComplex.h | 3 +- src/mainboard/pcengines/apu1/acpi/routing.asl | 2 +- src/mainboard/pcengines/apu1/board_info.txt | 4 +- src/mainboard/pcengines/apu1/buildOpts.c | 17 +- src/mainboard/pcengines/apu1/devicetree.cb | 62 +++-- src/mainboard/pcengines/apu1/dsdt.asl | 3 +- src/mainboard/pcengines/apu1/mainboard.c | 18 +- src/mainboard/pcengines/apu1/mptable.c | 2 + src/mainboard/pcengines/apu1/platform_cfg.h | 10 +- src/mainboard/pcengines/apu1/romstage.c | 5 + 17 files changed, 655 insertions(+), 65 deletions(-)
diff --git a/src/mainboard/pcengines/Kconfig b/src/mainboard/pcengines/Kconfig index 9fb477b..a20561b 100644 --- a/src/mainboard/pcengines/Kconfig +++ b/src/mainboard/pcengines/Kconfig @@ -11,6 +11,8 @@ config BOARD_PCENGINES_ALIX2D bool "ALIX.2D2 or 2D3" config BOARD_PCENGINES_ALIX6 bool "ALIX.6" +config BOARD_PCENGINES_APU1 + bool "APU1"
endchoice
@@ -18,6 +20,7 @@ source "src/mainboard/pcengines/alix1c/Kconfig" source "src/mainboard/pcengines/alix2c/Kconfig" source "src/mainboard/pcengines/alix2d/Kconfig" source "src/mainboard/pcengines/alix6/Kconfig" +source "src/mainboard/pcengines/apu1/Kconfig"
config MAINBOARD_VENDOR string diff --git a/src/mainboard/pcengines/apu1/BiosCallOuts.c b/src/mainboard/pcengines/apu1/BiosCallOuts.c index 74b9f67..d97fe22 100644 --- a/src/mainboard/pcengines/apu1/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu1/BiosCallOuts.c @@ -19,12 +19,14 @@
#include "AGESA.h" #include "amdlib.h" +#include <spd_cache.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "heapManager.h" #include "SB800.h" #include <stdlib.h>
static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr);
const BIOS_CALLOUT_STRUCT BiosCallouts[] = { @@ -32,7 +34,7 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, agesa_ReadSpd }, + {AGESA_READ_SPD, board_ReadSpd_from_cbfs }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GNB_PCIE_SLOT_RESET, agesa_NoopSuccess }, @@ -51,3 +53,26 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *Config ((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; return AGESA_SUCCESS; } + +static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status = AGESA_UNSUPPORTED; +#ifdef __PRE_RAM__ + AGESA_READ_SPD_PARAMS *info = ConfigPtr; + u8 index = 0; + + if (info->MemChannelId > 0) + return AGESA_UNSUPPORTED; + if (info->SocketId != 0) + return AGESA_UNSUPPORTED; + if (info->DimmId != 0) + return AGESA_UNSUPPORTED; + + /* Read index 0, first SPD_SIZE bytes of spd.bin file. */ + if (read_spd_from_cbfs((u8*)info->Buffer, index) < 0) + die("No SPD data\n"); + + Status = AGESA_SUCCESS; +#endif + return Status; +} diff --git a/src/mainboard/pcengines/apu1/HYNIX-H5TQ2G83CFR.spd.hex b/src/mainboard/pcengines/apu1/HYNIX-H5TQ2G83CFR.spd.hex new file mode 100644 index 0000000..c920e17 --- /dev/null +++ b/src/mainboard/pcengines/apu1/HYNIX-H5TQ2G83CFR.spd.hex @@ -0,0 +1,251 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2014 Sage Electronic Engineering, LLC. +# Copyright (C) 2014 Kyösti Mälkki kyosti.malkki@gmail.com +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +# HYNIX-H5TQ2G83CFR + +# SPD contents for APU 2GB DDR3 (1333MHz PC1333) soldered down +# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage +# bits[3:0]: 1 = 128 SPD Bytes Used +# bits[6:4]: 1 = 256 SPD Bytes Total +# bit7 : 0 = CRC covers bytes 0 ~ 125 +11 + +# 1 SPD Revision - +# 0x10 = Revision 1.0 +10 +# 2 Key Byte / DRAM Device Type +# bits[7:0]: 0x0b = DDR3 SDRAM +0B + +# 3 Key Byte / Module Type +# bits[3:0]: 3 = SO-DIMM +# bits[7:4]: reserved +03 + +# 4 SDRAM CHIP Density and Banks +# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip +# bits[6:4]: 0 = 3 (8 banks) +# bit7 : reserved +03 + +# 5 SDRAM Addressing +# bits[2:0]: 1 = 10 Column Address Bits +# bits[5:3]: 3 = 15 Row Address Bits +# bits[7:6]: reserved +19 + +# 6 Module Nominal Voltage, VDD +# bit0 : 0 = 1.5 V operable +# bit1 : 0 = NOT 1.35 V operable +# bit2 : 0 = NOT 1.25 V operable +# bits[7:3]: reserved +00 + +# 7 Module Organization +# bits[2:0]: 1 = 8 bits +# bits[5:3]: 0 = 1 Rank +# bits[7:6]: reserved +01 + +# 8 Module Memory Bus Width +# bits[2:0]: 3 = Primary bus width is 64 bits +# bits[4:3]: 0 = 0 bits (no bus width extension) +# bits[7:5]: reserved +03 + +# 9 Fine Timebase (FTB) Dividend / Divisor +# bits[3:0]: 0x01 divisor +# bits[7:4]: 0x01 dividend +# 1 / 1 = 1.0 ps +11 + +# 10 Medium Timebase (MTB) Dividend +# 11 Medium Timebase (MTB) Divisor +# 1 / 8 = .125 ns +01 08 + +# 12 SDRAM Minimum Cycle Time (tCKmin) +# 0x0c = tCKmin of 1.5 ns = in multiples of MTB +0C + +# 13 Reserved +00 + +# 14 CAS Latencies Supported, Least Significant Byte +# 15 CAS Latencies Supported, Most Significant Byte +# Cas Latencies of 11 - 5 are supported +7E 00 + +# 16 Minimum CAS Latency Time (tAAmin) +# 0x6C = 13.5ns - DDR3-1333 +6C + +# 17 Minimum Write Recovery Time (tWRmin) +# 0x78 = tWR of 15ns - All DDR3 speed grades +78 + +# 18 Minimum RAS# to CAS# Delay Time (tRCDmin) +# 0x6E = 13.5ns - DDR3-1333 +6C + +# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) +# 0x30 = 6ns +30 + +# 20 Minimum Row Precharge Delay Time (tRPmin) +# 0x6C = 13.5ns - DDR3-1333 +6C + +# 21 Upper Nibbles for tRAS and tRC +# bits[3:0]: tRAS most significant nibble = 1 (see byte 22) +# bits[7:4]: tRC most significant nibble = 1 (see byte 23) +11 + +# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB +# 0x120 = 36ns - DDR3-1333 (see byte 21) +20 + +# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB +# 0x28C = 49.5ns - DDR3-1333 +8C + +# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB +# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB +# 0x500 = 160ns - for 2 Gigabit chips +00 05 + +# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) +# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins +3C + +# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) +# 0x3c = 7.5ns - All DDR3 SDRAM speed bins +3C + +# 28 Upper Nibble for tFAWmin +# 29 Minimum Four Activate Window Delay Time (tFAWmin) +# 0x00F0 = 30ns - DDR3-1333, 1 KB page size +00 F0 + +# 30 SDRAM Optional Feature +# bit0 : 1= RZQ/6 supported +# bit1 : 1 = RZQ/7 supported +# bits[6:2]: reserved +# bit7 : 1 = DLL Off mode supported +83 + +# 31 SDRAM Thermal and Refresh Options +# bit0 : 1 = Temp up to 95c supported +# bit1 : 0 = 85-95c uses 2x refresh rate +# bit2 : 1 = Auto Self Refresh supported +# bit3 : 0 = no on die thermal sensor +# bits[6:4]: reserved +# bit7 : 0 = partial self refresh supported +05 + +# 32 Module Thermal Sensor +# 0 = Thermal sensor not incorporated onto this assembly +00 + +# 33 SDRAM Device Type +# bits[1:0]: 2 = Signal Loading +# bits[3:2]: reserved +# bits[6:4]: 4 = Die count +# bit7 : 0 = Standard Monolithic DRAM Device +42 + +# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) +# 35 Fine Offset for Minimum CAS Latency Time (tAAmin) +# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) +# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin) +# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin) +00 00 00 00 00 + +# 39 (reserved) +00 + +# 40 - 47 (reserved) +00 00 00 00 00 00 00 00 + +# 48 - 55 (reserved) +00 00 00 00 00 00 00 00 + +# 56 - 59 (reserved) +00 00 00 00 + +# 60 Raw Card Extension, Module Nominal Height +# bits[4:0]: 0 = <= 15mm tall +# bits[7:5]: 0 = raw card revision 0-3 +00 + +# 61 Module Maximum Thickness +# bits[3:0]: 0 = thickness front <= 1mm +# bits[7:4]: 0 = thinkness back <= 1mm +00 + +# 62 Reference Raw Card Used +# bits[4:0]: 0 = Reference Raw card A used +# bits[6:5]: 0 = revision 0 +# bit7 : 0 = Reference raw cards A through AL +00 + +# 63 Address Mapping from Edge Connector to DRAM +# bit0 : 0 = standard mapping (not mirrored) +# bits[7:1]: reserved +00 + +# 64 - 71 (reserved) +00 00 00 00 00 00 00 00 + +# 72 - 79 (reserved) +00 00 00 00 00 00 00 00 + +# 80 - 87 (reserved) +00 00 00 00 00 00 00 00 + +# 88 - 95 (reserved) +00 00 00 00 00 00 00 00 + +# 96 - 103 (reserved) +00 00 00 00 00 00 00 00 + +# 104 - 111 (reserved) +00 00 00 00 00 00 00 00 + +# 112 - 116 (reserved) +00 00 00 00 00 + +# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code +# 0x0001 = AMD +00 01 + +# 119 Module ID: Module Manufacturing Location - oem specified +00 + +# 120 Module ID: Module Manufacture Year in BCD +# 0x13 = 2013 +# 121 Module ID: Module Manufacture week +# 0x12 = 12th week +13 12 + +# 122 - 125: Module Serial Number +00 00 00 00 + +# 126 - 127: Cyclical Redundancy Code +00 00 diff --git a/src/mainboard/pcengines/apu1/HYNIX-H5TQ4G83MFR.spd.hex b/src/mainboard/pcengines/apu1/HYNIX-H5TQ4G83MFR.spd.hex new file mode 100644 index 0000000..7aa4634 --- /dev/null +++ b/src/mainboard/pcengines/apu1/HYNIX-H5TQ4G83MFR.spd.hex @@ -0,0 +1,253 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2014 Sage Electronic Engineering, LLC. +# Copyright (C) 2014 Kyösti Mälkki kyosti.malkki@gmail.com +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +# HYNIX-H5TQ4G83MFR + +# SPD contents for APU 2GB DDR3 (1333MHz PC1333) soldered down +# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage +# bits[3:0]: 1 = 128 SPD Bytes Used +# bits[6:4]: 1 = 256 SPD Bytes Total +# bit7 : 0 = CRC covers bytes 0 ~ 125 +11 + +# 1 SPD Revision - +# 0x10 = Revision 1.0 +10 +# 2 Key Byte / DRAM Device Type +# bits[7:0]: 0x0b = DDR3 SDRAM +0B + +# 3 Key Byte / Module Type +# bits[3:0]: 3 = SO-DIMM +# bits[7:4]: reserved +03 + +# 4 SDRAM CHIP Density and Banks +# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip +# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip +# bits[6:4]: 0 = 3 (8 banks) +# bit7 : reserved +04 + +# 5 SDRAM Addressing +# bits[2:0]: 1 = 10 Column Address Bits +# bits[5:3]: 3 = 15 Row Address Bits +# bits[5:3]: 4 = 16 Row Address Bits +# bits[7:6]: reserved +21 + +# 6 Module Nominal Voltage, VDD +# bit0 : 0 = 1.5 V operable +# bit1 : 0 = NOT 1.35 V operable +# bit2 : 0 = NOT 1.25 V operable +# bits[7:3]: reserved +00 + +# 7 Module Organization +# bits[2:0]: 1 = 8 bits +# bits[5:3]: 0 = 1 Rank +# bits[7:6]: reserved +01 + +# 8 Module Memory Bus Width +# bits[2:0]: 3 = Primary bus width is 64 bits +# bits[4:3]: 0 = 0 bits (no bus width extension) +# bits[7:5]: reserved +03 + +# 9 Fine Timebase (FTB) Dividend / Divisor +# bits[3:0]: 0x01 divisor +# bits[7:4]: 0x01 dividend +# 1 / 1 = 1.0 ps +11 + +# 10 Medium Timebase (MTB) Dividend +# 11 Medium Timebase (MTB) Divisor +# 1 / 8 = .125 ns +01 08 + +# 12 SDRAM Minimum Cycle Time (tCKmin) +# 0x0c = tCKmin of 1.5 ns = in multiples of MTB +0C + +# 13 Reserved +00 + +# 14 CAS Latencies Supported, Least Significant Byte +# 15 CAS Latencies Supported, Most Significant Byte +# Cas Latencies of 11 - 5 are supported +7E 00 + +# 16 Minimum CAS Latency Time (tAAmin) +# 0x6C = 13.5ns - DDR3-1333 +6C + +# 17 Minimum Write Recovery Time (tWRmin) +# 0x78 = tWR of 15ns - All DDR3 speed grades +78 + +# 18 Minimum RAS# to CAS# Delay Time (tRCDmin) +# 0x6E = 13.5ns - DDR3-1333 +6C + +# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) +# 0x30 = 6ns +30 + +# 20 Minimum Row Precharge Delay Time (tRPmin) +# 0x6C = 13.5ns - DDR3-1333 +6C + +# 21 Upper Nibbles for tRAS and tRC +# bits[3:0]: tRAS most significant nibble = 1 (see byte 22) +# bits[7:4]: tRC most significant nibble = 1 (see byte 23) +11 + +# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB +# 0x120 = 36ns - DDR3-1333 (see byte 21) +20 + +# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB +# 0x28C = 49.5ns - DDR3-1333 +8C + +# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB +# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB +# 0x500 = 160ns - for 2 Gigabit chips +00 05 + +# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) +# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins +3C + +# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) +# 0x3c = 7.5ns - All DDR3 SDRAM speed bins +3C + +# 28 Upper Nibble for tFAWmin +# 29 Minimum Four Activate Window Delay Time (tFAWmin) +# 0x00F0 = 30ns - DDR3-1333, 1 KB page size +00 F0 + +# 30 SDRAM Optional Feature +# bit0 : 1= RZQ/6 supported +# bit1 : 1 = RZQ/7 supported +# bits[6:2]: reserved +# bit7 : 1 = DLL Off mode supported +83 + +# 31 SDRAM Thermal and Refresh Options +# bit0 : 1 = Temp up to 95c supported +# bit1 : 0 = 85-95c uses 2x refresh rate +# bit2 : 1 = Auto Self Refresh supported +# bit3 : 0 = no on die thermal sensor +# bits[6:4]: reserved +# bit7 : 0 = partial self refresh supported +05 + +# 32 Module Thermal Sensor +# 0 = Thermal sensor not incorporated onto this assembly +00 + +# 33 SDRAM Device Type +# bits[1:0]: 2 = Signal Loading +# bits[3:2]: reserved +# bits[6:4]: 4 = Die count +# bit7 : 0 = Standard Monolithic DRAM Device +42 + +# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) +# 35 Fine Offset for Minimum CAS Latency Time (tAAmin) +# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) +# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin) +# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin) +00 00 00 00 00 + +# 39 (reserved) +00 + +# 40 - 47 (reserved) +00 00 00 00 00 00 00 00 + +# 48 - 55 (reserved) +00 00 00 00 00 00 00 00 + +# 56 - 59 (reserved) +00 00 00 00 + +# 60 Raw Card Extension, Module Nominal Height +# bits[4:0]: 0 = <= 15mm tall +# bits[7:5]: 0 = raw card revision 0-3 +00 + +# 61 Module Maximum Thickness +# bits[3:0]: 0 = thickness front <= 1mm +# bits[7:4]: 0 = thinkness back <= 1mm +00 + +# 62 Reference Raw Card Used +# bits[4:0]: 0 = Reference Raw card A used +# bits[6:5]: 0 = revision 0 +# bit7 : 0 = Reference raw cards A through AL +00 + +# 63 Address Mapping from Edge Connector to DRAM +# bit0 : 0 = standard mapping (not mirrored) +# bits[7:1]: reserved +00 + +# 64 - 71 (reserved) +00 00 00 00 00 00 00 00 + +# 72 - 79 (reserved) +00 00 00 00 00 00 00 00 + +# 80 - 87 (reserved) +00 00 00 00 00 00 00 00 + +# 88 - 95 (reserved) +00 00 00 00 00 00 00 00 + +# 96 - 103 (reserved) +00 00 00 00 00 00 00 00 + +# 104 - 111 (reserved) +00 00 00 00 00 00 00 00 + +# 112 - 116 (reserved) +00 00 00 00 00 + +# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code +# 0x0001 = AMD +00 01 + +# 119 Module ID: Module Manufacturing Location - oem specified +00 + +# 120 Module ID: Module Manufacture Year in BCD +# 0x13 = 2013 +# 121 Module ID: Module Manufacture week +# 0x12 = 12th week +13 12 + +# 122 - 125: Module Serial Number +00 00 00 00 + +# 126 - 127: Cyclical Redundancy Code +00 00 diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index ade4b72..8b87961 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -2,6 +2,7 @@ # This file is part of the coreboot project. # # Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2014 Kyösti Mälkki kyosti.malkki@gmail.com # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -17,28 +18,29 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA #
-if BOARD_AMD_PERSIMMON +if BOARD_PCENGINES_APU1
config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 + select SUPERIO_NUVOTON_NCT5104D select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_ACPI_RESUME + #select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_4096 - select GFXUMA + select BOARD_ROMSIZE_KB_2048 + select SPD_CACHE
config MAINBOARD_DIR string - default amd/persimmon + default pcengines/apu1
config MAINBOARD_PART_NUMBER string - default "Persimmon" + default "APU1"
config HW_MEM_HOLE_SIZEK hex @@ -81,4 +83,4 @@ config DRIVERS_PS2_KEYBOARD bool default n
-endif # BOARD_AMD_PERSIMMON +endif # BOARD_PCENGINES_APU1 diff --git a/src/mainboard/pcengines/apu1/Makefile.inc b/src/mainboard/pcengines/apu1/Makefile.inc index c82834c..7fbed57 100644 --- a/src/mainboard/pcengines/apu1/Makefile.inc +++ b/src/mainboard/pcengines/apu1/Makefile.inc @@ -2,6 +2,8 @@ # This file is part of the coreboot project. # # Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2013 Sage Electronic Engineering, LLC +# Copyright (C) 2014 Kyösti Mälkki kyosti.malkki@gmail.com # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -31,3 +33,23 @@ romstage-y += PlatformGnbPcie.c ramstage-y += buildOpts.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c + +## DIMM SPD for on-board memory +SPD_BIN = $(obj)/spd.bin + +# Order of names in SPD_SOURCES is important! +SPD_SOURCES = HYNIX-H5TQ2G83CFR HYNIX-H5TQ4G83MFR + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) + +# Include spd rom data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do echo -e -n "\x$$c"; \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := 0xab diff --git a/src/mainboard/pcengines/apu1/PlatformGnbPcie.c b/src/mainboard/pcengines/apu1/PlatformGnbPcie.c index f2fe96b..26cdc4a 100644 --- a/src/mainboard/pcengines/apu1/PlatformGnbPcie.c +++ b/src/mainboard/pcengines/apu1/PlatformGnbPcie.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,8 +24,6 @@ #include <northbridge/amd/agesa/agesawrapper.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
-#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE - /** * OemCustomizeInitEarly * @@ -53,25 +52,25 @@ PCIe_PORT_DESCRIPTOR PortList [] = { { 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46) + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) }, // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) { 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46) + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) }, // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) { 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46) + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) }, // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) }, // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) { @@ -84,18 +83,11 @@ PCIe_PORT_DESCRIPTOR PortList [] = { PCIe_DDI_DESCRIPTOR DdiList [] = { // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) { - 0, //Descriptor flags + DESCRIPTOR_TERMINATE_LIST, //Descriptor flags PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) - {ConnectorTypeLvds, Aux1, Hdp1} + {ConnectorTypeDP, Aux1, Hdp1} }, - // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) - { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) - {ConnectorTypeDP, Aux2, Hdp2} - } };
PCIe_COMPLEX_DESCRIPTOR Brazos = { diff --git a/src/mainboard/pcengines/apu1/PlatformGnbPcieComplex.h b/src/mainboard/pcengines/apu1/PlatformGnbPcieComplex.h index 4a01875..89a41a1 100644 --- a/src/mainboard/pcengines/apu1/PlatformGnbPcieComplex.h +++ b/src/mainboard/pcengines/apu1/PlatformGnbPcieComplex.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -50,7 +51,7 @@ #define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 0 //0:Disable 1:Enable +#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 #define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) diff --git a/src/mainboard/pcengines/apu1/acpi/routing.asl b/src/mainboard/pcengines/apu1/acpi/routing.asl index 0395700..cd38608 100644 --- a/src/mainboard/pcengines/apu1/acpi/routing.asl +++ b/src/mainboard/pcengines/apu1/acpi/routing.asl @@ -73,7 +73,7 @@ Scope(_SB) {
/* OHCI, dev 18, 19, 22 func 0 * EHCI, dev 18, 19, 22 func 2 */ - Package(){0x0012FFFF, 0, INTC, 0 }, /* Dev 12, INTA, handled by INTC device, Global */ + Package(){0x0012FFFF, 0, INTC, 0 }, /* Dev 12, INTA, handled by INTC device, Global */ Package(){0x0012FFFF, 1, INTB, 0 }, /* Dev 12, INTB, handled by INTB device, Global */
Package(){0x0013FFFF, 0, INTC, 0 }, diff --git a/src/mainboard/pcengines/apu1/board_info.txt b/src/mainboard/pcengines/apu1/board_info.txt index 85cb19a..6c824df 100644 --- a/src/mainboard/pcengines/apu1/board_info.txt +++ b/src/mainboard/pcengines/apu1/board_info.txt @@ -1,5 +1,5 @@ -Board name: DBFT1-00-EVAL-KT (Persimmon) -Category: eval +Board name: APU1 +Category: half ROM protocol: SPI ROM socketed: n Flashrom support: y diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c index 9cf2a19..cfc9d3d 100644 --- a/src/mainboard/pcengines/apu1/buildOpts.c +++ b/src/mainboard/pcengines/apu1/buildOpts.c @@ -209,7 +209,7 @@ //#define BLDCFG_ECC_SYNC_FLOOD 0 //#define BLDCFG_ECC_SYMBOL_SIZE 0 //#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO +#define BLDCFG_UMA_ALLOCATION_MODE UMA_NONE #define BLDCFG_UMA_ALLOCATION_SIZE 0 #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE #define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED @@ -382,8 +382,19 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { // Byte6Seed, Byte7Seed, ByteEccSeed) // Specifies the write leveling seed for a channel of a socket. // - NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), - NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), + + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, TWO_DIMM), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, ONE_DIMM), + + // APU soldered down memory uses memory CLK0 and CLK1 on CS0 + MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + + // APU soldered down memory requires different seeds +#define WLSEED 0x08 +#define RXSEED 0x40 + WRITE_LEVELING_SEED(ANY_SOCKET, ANY_CHANNEL, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED), + HW_RXEN_SEED( ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED), + PSO_END };
diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb index 2f6bb14..5f6f9c9 100644 --- a/src/mainboard/pcengines/apu1/devicetree.cb +++ b/src/mainboard/pcengines/apu1/devicetree.cb @@ -2,6 +2,7 @@ # This file is part of the coreboot project. # # Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2014 Kyösti Mälkki kyosti.malkki@gmail.com # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -28,44 +29,65 @@ chip northbridge/amd/agesa/family14/root_complex # device pci 18.0 on # northbridge chip northbridge/amd/agesa/family14 # PCI side of HT root complex device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] + device pci 1.0 off end # Internal Graphics P2P bridge 0x980[2456] device pci 4.0 on end # PCIE P2P bridge on-board NIC - device pci 5.0 off end # PCIE P2P bridge + device pci 5.0 on end # PCIE P2P bridge device pci 6.0 on end # PCIE P2P bridge PCIe slot - device pci 7.0 off end # PCIE P2P bridge - device pci 8.0 off end # NB/SB Link P2P bridge + device pci 7.0 on end # PCIE P2P bridge + device pci 8.0 on end # NB/SB Link P2P bridge end # agesa northbridge
chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus device pci 11.0 on end # SATA device pci 12.0 on end # OHCI USB 0-4 + device pci 12.1 on end # OHCI USB 0-4 device pci 12.2 on end # EHCI USB 0-4 device pci 13.0 on end # OHCI USB 5-9 + device pci 13.1 on end # OHCI USB 5-9 device pci 13.2 on end # EHCI USB 5-9 device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d + chip superio/nuvoton/nct5104d + register "irq_trigger_type" = "0" + device pnp 2e.0 off end + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.10 off + io 0x60 = 0x3e8 + irq 0x70 = 4 + end + device pnp 2e.11 off + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 2e.8 off end + device pnp 2e.f off end + device pnp 2e.7 off end + device pnp 2e.107 off end + device pnp 2e.607 off end + device pnp 2e.e off end + end end #LPC device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 off end # OHCI FS/LS USB - device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) - device pci 15.0 off end # PCIe PortA + device pci 14.5 on end # OHCI FS/LS USB + #device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) + device pci 15.0 on end # PCIe PortA device pci 15.1 off end # PCIe PortB device pci 15.2 off end # PCIe PortC device pci 15.3 off end # PCIe PortD - device pci 16.0 off end # OHCI USB 10-13 - device pci 16.2 off end # EHCI USB 10-13 - register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) + device pci 16.0 on end # OHCI USB 10-13 + device pci 16.2 on end # EHCI USB 10-13 + register "gpp_configuration" = "0" register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb800 # end # device pci 18.0 # These seem unnecessary @@ -78,12 +100,6 @@ chip northbridge/amd/agesa/family14/root_complex device pci 18.6 on end device pci 18.7 on end
- register "spdAddrLookup" = " - { - { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" - end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/pcengines/apu1/dsdt.asl b/src/mainboard/pcengines/apu1/dsdt.asl index 25520b2..d3b2920 100644 --- a/src/mainboard/pcengines/apu1/dsdt.asl +++ b/src/mainboard/pcengines/apu1/dsdt.asl @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,7 +23,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ + "PCENG ", /* OEMID */ "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 1096f05..cf0d823 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -48,7 +48,7 @@ void set_pcie_dereset(void); * These values are used by the PCI configuration space, * MP Tables. TODO: Make ACPI use these values too. * - * The Persimmon PCI INTA/B/C/D pins are connected to + * The PCI INTA/B/C/D pins are connected to * FCH pins INTE/F/G/H on the schematic so these need * to be routed as well. */ @@ -56,13 +56,13 @@ static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { /* INTA# - INTH# */ [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x08] = 0x00,0xF0,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + [0x08] = 0x00,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */ [0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F, /* IMC INT0 - 5 */ [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, /* USB Devs 18/19/20/22 INTA-C */ - [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A, + [0x30] = 0x0A,0x0B,0x0A,0x0B,0x1F,0x1F,0x0A, /* IDE, SATA */ [0x40] = 0x0B,0x0B, /* GPPInt0 - 3 */ @@ -97,8 +97,8 @@ static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { * use PIC IRQ 10 if it uses PIN A for its hardware INT. */ /* - * Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H - * but because PCI INT_PIN swizzling isnt implemented to match + * The PCI slot INTA/B/C/D connected to PIRQE/F/G/H + * but because of PCI INT_PIN swizzle isnt implemented to match * the IDSEL (dev 3) of the slot, the table is adjusted for the * swizzle and INTA is connected to PIRQH so PINA/B/C/D on * off-chip devices should get mapped to PIRQH/E/F/G. @@ -107,7 +107,9 @@ static const struct pirq_struct mainboard_pirq_data[] = { /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ {GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 04.0 */ - {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe bdg: 06.0 */ + {NB_PCIE_PORT2_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 05.0 */ + {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 06.0 */ + {NB_PCIE_PORT4_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* miniPCIe: 07.0 */ {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ @@ -118,6 +120,7 @@ static const struct pirq_struct mainboard_pirq_data[] = { {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCI bdg: 14.4 */ {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4: 14.5 */ + {SB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* miniPCIe: 15.0 */ {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */ {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */ }; @@ -147,7 +150,6 @@ void set_pcie_dereset(void) { }
- /********************************************** * Enable the dedicated functions of the board. **********************************************/ diff --git a/src/mainboard/pcengines/apu1/mptable.c b/src/mainboard/pcengines/apu1/mptable.c index 1227d89..4686d62 100644 --- a/src/mainboard/pcengines/apu1/mptable.c +++ b/src/mainboard/pcengines/apu1/mptable.c @@ -111,6 +111,8 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE */ PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ + PCI_INT(0x3, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ + PCI_INT(0x4, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
/* PCI slots */ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); diff --git a/src/mainboard/pcengines/apu1/platform_cfg.h b/src/mainboard/pcengines/apu1/platform_cfg.h index 097c835..2efe905 100644 --- a/src/mainboard/pcengines/apu1/platform_cfg.h +++ b/src/mainboard/pcengines/apu1/platform_cfg.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,6 +22,9 @@ #ifndef _PLATFORM_CFG_H_ #define _PLATFORM_CFG_H_
+/* APU has no legacy P/S2 controller */ +#define LEGACY_FREE 0 /* setting legacy free disables I/O access to 0x3F8 */ + /** * @def BIOS_SIZE * BIOS_SIZE_{1,2,4,8,16}M @@ -75,7 +79,7 @@ * PCI SLOT 3 define at BIT3 * PCI SLOT 4 define at BIT4 */ -#define PCI_CLOCK_CTRL 0x07 +#define PCI_CLOCK_CTRL 0x1F
/** * @def SATA_CONTROLLER @@ -182,7 +186,7 @@ * GPP_CFGMODE_X2110 * GPP_CFGMODE_X1111 */ -#define GPP_CFGMODE GPP_CFGMODE_X1111 +#define GPP_CFGMODE GPP_CFGMODE_X4000
/** * @def NB_SB_GEN2 @@ -203,7 +207,7 @@ * TRUE - ports visible always, even port empty * FALSE - ports invisible if port empty */ -#define SB_GPP_UNHIDE_PORTS FALSE +#define SB_GPP_UNHIDE_PORTS TRUE
/** * @def GEC_CONFIG diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c index d90a39d..c555536 100644 --- a/src/mainboard/pcengines/apu1/romstage.c +++ b/src/mainboard/pcengines/apu1/romstage.c @@ -39,7 +39,11 @@ #include "cbmem.h" #include <cpu/amd/mtrr.h> #include <cpu/amd/agesa/s3_resume.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct5104d/nct5104d.h>
+#define SIO_PORT 0x2e +#define SERIAL_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -62,6 +66,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init();
post_code(0x31); + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); }
-
Kyösti Mälkki