Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE

[Lean Sheng Tan (Code Review)]

Attention is currently required from: Arthur Heymans, Nico Huber, Martin Roth, Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Angel Pons, Subrata Banik, Michael Niewöhner, Patrick Rudolph, Felix Held.
Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 )

Change subject: soc/intel/elkhartlake: Introduce Intel PSE
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Patch Set 55:

(1 comment)

File src/soc/intel/elkhartlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/55367/comment/05fa6ce4_416e5d95 
PS52, Line 129: /* Set the ownership of these devices to PSE */
              : 		params->PchPseDmaEnable[0] = PSE_Owned;
              : 		params->PchPseUartEnable[2] = PSE_Owned;
              : 		params->PchPseHsuartEnable[2] = PSE_Owned;
              : 		params->PchPseI2cEnable[2] = PSE_Owned;
              : 		params->PchPseTimedGpioEnable[0] = PSE_Owned;
              : 		params->PchPseTimedGpioEnable[1] = PSE_Owned;
              : 		/* Disable PSE DMA Sideband Interrupt for DMA 0 */
              : 		params->PchPseDmaSbInterruptEnable[0] = 0;
              : 		/* Set the log output to PSE UART 2 */
              : 		params->PchPseLogOutputChannel = 3;
> Without knowing the reasons why these settings are required, I'm afraid I can't think of a better ap […]

Hi Angel, sorry I cannot do much about it for now :( PSE requires these configs to work properly. I hate this too, should have raise this to PSE team much earlier time. For now we can do more about it when PSE code is open sourced in the future.. Lets see.