[S] Change in coreboot[master]: soc/intel/meteorlake: Add timestamp for cse_fw_sync The patch add tim...

[Dinesh Gehlot (Code Review)]

Dinesh Gehlot has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70172 )

Change subject: soc/intel/meteorlake: Add timestamp for cse_fw_sync The patch add timestamp around cse_fw_sync(). BUG=none TEST=Verified on Brya, cbmem -t:  948:starting CSE firmware sync                        1,340,551 (50,657)  949:finished CSE firmware sync                        1,379,348 (38,797) Port of commit 7c6dd796f26f (“soc/intel/alderlake: Add timestamp for cse_fw_sync”) \
......................................................................

soc/intel/meteorlake: Add timestamp for cse_fw_sync The patch add timestamp around cse_fw_sync(). BUG=none TEST=Verified on Brya, cbmem -t:  948:starting CSE firmware sync                        1,340,551 (50,657)  949:finished CSE firmware sync                        1,379,348 (38,797) Port of commit 7c6dd796f26f (“soc/intel/alderlake: Add timestamp for cse_fw_sync”) \

Signed-off-by: Dinesh Gehlot 
Change-Id: I6cfbf84018e312fbf9482f0fba05b444603cd4b9
---
M src/soc/intel/meteorlake/romstage/romstage.c
1 file changed, 15 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/70172/1

diff --git a/src/soc/intel/meteorlake/romstage/romstage.c b/src/soc/intel/meteorlake/romstage/romstage.c
index bac3caf..ba0079c 100644
--- a/src/soc/intel/meteorlake/romstage/romstage.c
+++ b/src/soc/intel/meteorlake/romstage/romstage.c
@@ -15,6 +15,7 @@
 #include <soc/pm.h>
 #include <soc/romstage.h>
 #include <soc/soc_chip.h>
+#include <timestamp.h>
 #include <string.h>

#define FSP_SMBIOS_MEMORY_INFO_GUID	\
@@ -130,8 +131,11 @@

s3wake = pmc_fill_power_state(ps) == ACPI_S3;
    if (!s3wake) {
-		if (CONFIG(SOC_INTEL_CSE_LITE_SKU))
+		if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) {
+			timestamp_add_now(TS_CSE_FW_SYNC_START);
    		cse_fw_sync();
+			timestamp_add_now(TS_CSE_FW_SYNC_END);
+		}
    }

/*