Attention is currently required from: Arthur Heymans. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63550 )
Change subject: soc/intel/fast_spi.c: Use smarter mtrr code in ramstage ......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
I will test this CL once again.
here is my feedback.
1. MTRR snapshot with this CL that uses `mtrr_use_temp_range`
`mtrr_use_temp_range` function will clear the previous
Every time BIOS calls mtrr_use_temp_range, it will get a fresh new addr_space see this https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thir...
so `fast_spi_enable_cache_range` tries to allocate BIOS and ext BIOS region by using mtrr_use_temp_range, but eventually, only ext BIOS region is allocated in MTRR since mtrr_use_temp_range doesn't keep the addr_space last time it's called(for BIOS region)
check this, only ext BIOS region is part of MTRR snapshot not the BIOS region unfortunately.
[DEBUG] 0x0000000000000006: PHYBASE0: Address = 0x0000000000000000, WB [DEBUG] 0x00003fff80000800: PHYMASK0: Length = 0x0000000080000000, Valid [DEBUG] 0x0000000077000000: PHYBASE1: Address = 0x0000000077000000, UC [DEBUG] 0x00003fffff000800: PHYMASK1: Length = 0x0000000001000000, Valid [DEBUG] 0x0000000078000000: PHYBASE2: Address = 0x0000000078000000, UC [DEBUG] 0x00003ffff8000800: PHYMASK2: Length = 0x0000000008000000, Valid [DEBUG] 0x00000000f9000005: PHYBASE3: Address = 0x00000000f9000000, WP [DEBUG] 0x00003fffff000800: PHYMASK3: Length = 0x0000000001000000, Valid [DEBUG] 0x0000000100000006: PHYBASE4: Address = 0x0000000100000000, WB [DEBUG] 0x00003fff00000800: PHYMASK4: Length = 0x0000000100000000, Valid [DEBUG] 0x0000000200000006: PHYBASE5: Address = 0x0000000200000000, WB [DEBUG] 0x00003fff80000800: PHYMASK5: Length = 0x0000000080000000, Valid [DEBUG] 0x000000027fc00000: PHYBASE6: Address = 0x000000027fc00000, UC [DEBUG] 0x00003fffffc00800: PHYMASK6: Length = 0x0000000000400000, Valid [DEBUG] 0x0000000000000000: PHYBASE7 [DEBUG] 0x0000000000000000: PHYMASK7: Disabled [DEBUG] 0x0000000000000000: PHYBASE8 [DEBUG] 0x0000000000000000: PHYMASK8: Disabled [DEBUG] 0x0000000000000000: PHYBASE9 [DEBUG] 0x0000000000000000: PHYMASK9: Disabled
2. MTRR snapshot CB:63492
Before clearing the temp MTRRs, you can see those rom cache MTRRs are not applied.
[DEBUG] 0x0000000000000006: PHYBASE0: Address = 0x0000000000000000, WB [DEBUG] 0x00003fff80000800: PHYMASK0: Length = 0x0000000080000000, Valid [DEBUG] 0x0000000077000000: PHYBASE1: Address = 0x0000000077000000, UC [DEBUG] 0x00003fffff000800: PHYMASK1: Length = 0x0000000001000000, Valid [DEBUG] 0x0000000078000000: PHYBASE2: Address = 0x0000000078000000, UC [DEBUG] 0x00003ffff8000800: PHYMASK2: Length = 0x0000000008000000, Valid [DEBUG] 0x0000000090000001: PHYBASE3: Address = 0x0000000090000000, WC [DEBUG] 0x00003ffff0000800: PHYMASK3: Length = 0x0000000010000000, Valid [DEBUG] 0x0000000100000006: PHYBASE4: Address = 0x0000000100000000, WB [DEBUG] 0x00003fff00000800: PHYMASK4: Length = 0x0000000100000000, Valid [DEBUG] 0x0000000200000006: PHYBASE5: Address = 0x0000000200000000, WB [DEBUG] 0x00003fff80000800: PHYMASK5: Length = 0x0000000080000000, Valid [DEBUG] 0x000000027fc00000: PHYBASE6: Address = 0x000000027fc00000, UC [DEBUG] 0x00003fffffc00800: PHYMASK6: Length = 0x0000000000400000, Valid [DEBUG] 0x00000000ff000005: PHYBASE7: Address = 0x00000000ff000000, WP [DEBUG] 0x00003fffff000800: PHYMASK7: Length = 0x0000000001000000, Valid [DEBUG] 0x00000000f9000005: PHYBASE8: Address = 0x00000000f9000000, WP [DEBUG] 0x00003fffff000800: PHYMASK8: Length = 0x0000000001000000, Valid [DEBUG] 0x0000000000000000: PHYBASE9 [DEBUG] 0x0000000000000000: PHYMASK9: Disabled
After clearing the temp MTRRs (prior to boot to payload)
[DEBUG] 0x0000000000000006: PHYBASE0: Address = 0x0000000000000000, WB [DEBUG] 0x00003fff80000800: PHYMASK0: Length = 0x0000000080000000, Valid [DEBUG] 0x0000000077000000: PHYBASE1: Address = 0x0000000077000000, UC [DEBUG] 0x00003fffff000800: PHYMASK1: Length = 0x0000000001000000, Valid [DEBUG] 0x0000000078000000: PHYBASE2: Address = 0x0000000078000000, UC [DEBUG] 0x00003ffff8000800: PHYMASK2: Length = 0x0000000008000000, Valid [DEBUG] 0x0000000090000001: PHYBASE3: Address = 0x0000000090000000, WC [DEBUG] 0x00003ffff0000800: PHYMASK3: Length = 0x0000000010000000, Valid [DEBUG] 0x0000000100000006: PHYBASE4: Address = 0x0000000100000000, WB [DEBUG] 0x00003fff00000800: PHYMASK4: Length = 0x0000000100000000, Valid [DEBUG] 0x0000000200000006: PHYBASE5: Address = 0x0000000200000000, WB [DEBUG] 0x00003fff80000800: PHYMASK5: Length = 0x0000000080000000, Valid [DEBUG] 0x000000027fc00000: PHYBASE6: Address = 0x000000027fc00000, UC [DEBUG] 0x00003fffffc00800: PHYMASK6: Length = 0x0000000000400000, Valid [DEBUG] 0x0000000000000000: PHYBASE7 [DEBUG] 0x0000000000000000: PHYMASK7: Disabled [DEBUG] 0x0000000000000000: PHYBASE8 [DEBUG] 0x0000000000000000: PHYMASK8: Disabled [DEBUG] 0x0000000000000000: PHYBASE9 [DEBUG] 0x0000000000000000: PHYMASK9: Disabled
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Subrata Banik (Code Review)