[XS] Change in coreboot[main]: soc/intel/common/block/power_limit: Disable RAPL via MSR completely

[Mario Scheithauer (Code Review)]

Attention is currently required from: Johannes Hahn, Uwe Poeche, Werner Zeh.

Mario Scheithauer has posted comments on this change by Johannes Hahn. ( https://review.coreboot.org/c/coreboot/+/85606?usp=email )

The change is no longer submittable: All-Comments-Resolved and Code-Review are unsatisfied now.

Change subject: soc/intel/common/block/power_limit: Disable RAPL via MSR completely
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Patch Set 5: Code-Review+1

(1 comment)

File src/soc/intel/common/block/power_limit/power_limit.c:

https://review.coreboot.org/c/coreboot/+/85606/comment/403e3a63_bef443b9?usp... :
PS5, Line 97: msr = rdmsr(MSR_PKG_POWER_LIMIT);
Maybe one more thing...
If you set the whole register to '0', you can skip the previous read.