huayang duan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32243
Change subject: mediatek/mt8183: add support for SAMSUNG EMCP DDR ......................................................................
mediatek/mt8183: add support for SAMSUNG EMCP DDR
BUG=b:80501386 BRANCH=none TEST=Boots correctly on EMCP DRAM
Change-Id: I5fcc8673a2fbd7ec3a8776ab61c57f8903ddda20 --- M src/mainboard/google/kukui/sdram_configs.c M src/mainboard/google/kukui/sdram_params/Makefile.inc A src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c 4 files changed, 44 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/32243/1
diff --git a/src/mainboard/google/kukui/sdram_configs.c b/src/mainboard/google/kukui/sdram_configs.c old mode 100644 new mode 100755 index cbfb08d..ca74fa7 --- a/src/mainboard/google/kukui/sdram_configs.c +++ b/src/mainboard/google/kukui/sdram_configs.c @@ -21,6 +21,7 @@ static const char *const sdram_configs[] = { [1] = "sdram-lpddr4x-H9HCNNNCPMALHR-4GB", [2] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB", + [3] = "sdram-lpddr4x-KMDP6001DA-B425-4GB", };
static struct sdram_params params; diff --git a/src/mainboard/google/kukui/sdram_params/Makefile.inc b/src/mainboard/google/kukui/sdram_params/Makefile.inc old mode 100644 new mode 100755 index 1e11140..d685b1a --- a/src/mainboard/google/kukui/sdram_params/Makefile.inc +++ b/src/mainboard/google/kukui/sdram_params/Makefile.inc @@ -1,6 +1,7 @@ sdram-params := sdram-params += sdram-lpddr4x-H9HCNNNCPMALHR-4GB sdram-params += sdram-lpddr4x-MT53E1G32D4NQ-4GB +sdram-params += sdram-lpddr4x-KMDP6001DA-B425-4GB
$(foreach params,$(sdram-params), \ $(eval cbfs-files-y += $(params)) \ diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c new file mode 100755 index 0000000..1e0c362 --- /dev/null +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/emi.h> + +struct sdram_params params = { + .impedance = { + [ODT_OFF] = {0x9, 0x7, 0x0, 0xF}, + [ODT_ON] = {0xA, 0x9, 0x0, 0xE} + }, + .wr_level = { + [CHANNEL_A] = { {0x21, 0x21}, {0x20, 0x20} }, + [CHANNEL_B] = { {0x1E, 0x1F}, {0x1D, 0x1E} } + }, + .cbt_cs = { + [CHANNEL_A] = {0x1, 0x1}, + [CHANNEL_B] = {0x2, 0x2} + }, + .cbt_mr12 = { + [CHANNEL_A] = {0x56, 0x56}, + [CHANNEL_B] = {0x58, 0x5C} + }, + .emi_cona_val = 0xF053F154, + .emi_conh_val = 0x44440003, + .emi_conf_val = 0x00421000, + .chn_emi_cona_val = {0x0444F051, 0x0444F051}, + .cbt_mode_extern = CBT_NORMAL_MODE, + .delay_cell_unit = 868, +}; diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c old mode 100644 new mode 100755 index 11a46bb..1fefd34 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -32,7 +32,7 @@
enum { FIRST_DQ_DELAY = 0, - FIRST_DQS_DELAY = -10, + FIRST_DQS_DELAY = -16, MAX_DQDLY_TAPS = 16, MAX_RX_DQDLY_TAPS = 63, };
huayang duan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32243 )
Change subject: mediatek/mt8183: add support for SAMSUNG EMCP DDR ......................................................................
Patch Set 1: Code-Review+1
You-Cheng Syu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32243 )
Change subject: mediatek/mt8183: add support for SAMSUNG EMCP DDR ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/32243/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32243/1//COMMIT_MSG@14 PS1, Line 14: Missing Signed-off-by line
Hello Julius Werner, You-Cheng Syu, Tristan Hsieh, Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32243
to look at the new patch set (#2).
Change subject: mediatek/mt8183: add SAMSUNG and MICRON EMCP LPDDR4X support ......................................................................
mediatek/mt8183: add SAMSUNG and MICRON EMCP LPDDR4X support
add SAMSUNG KMDP6001DA-B425 EMCP LPDDR4X support add MICRON MT29VZZZAD8DQKSL EMCP LPDDR4X support
BUG=b:80501386 BRANCH=none TEST=Boots correctly on EMCP DRAM
Change-Id: I5fcc8673a2fbd7ec3a8776ab61c57f8903ddda20 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/mainboard/google/kukui/sdram_configs.c M src/mainboard/google/kukui/sdram_params/Makefile.inc A src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c A src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c 5 files changed, 87 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/32243/2
huayang duan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32243 )
Change subject: mediatek/mt8183: add SAMSUNG and MICRON EMCP LPDDR4X support ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/32243/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32243/1//COMMIT_MSG@14 PS1, Line 14:
Missing Signed-off-by line
Done
Hello Julius Werner, You-Cheng Syu, Tristan Hsieh, Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32243
to look at the new patch set (#3).
Change subject: mediatek/mt8183: add SAMSUNG and MICRON EMCP LPDDR4X support ......................................................................
mediatek/mt8183: add SAMSUNG and MICRON EMCP LPDDR4X support
add SAMSUNG KMDP6001DA-B425 EMCP LPDDR4X support add MICRON MT29VZZZAD8DQKSL EMCP LPDDR4X support
BUG=b:80501386 BRANCH=none TEST=Boots correctly on EMCP DRAM
Change-Id: I5fcc8673a2fbd7ec3a8776ab61c57f8903ddda20 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/mainboard/google/kukui/sdram_configs.c M src/mainboard/google/kukui/sdram_params/Makefile.inc A src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c A src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c 5 files changed, 87 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/32243/3
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32243 )
Change subject: mediatek/mt8183: add SAMSUNG and MICRON EMCP LPDDR4X support ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/32243/3/src/soc/mediatek/mt8183/dramc_pi_cal... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/#/c/32243/3/src/soc/mediatek/mt8183/dramc_pi_cal... PS3, Line 35: -16 why is this changed, and will this be a problem for other existing DRAM modules?
I think you should either move this to a standalone patch, or explain why this is changed in commit message.
huayang duan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32243 )
Change subject: mediatek/mt8183: add SAMSUNG and MICRON EMCP LPDDR4X support ......................................................................
Patch Set 3: Code-Review+1
(1 comment)
https://review.coreboot.org/#/c/32243/3/src/soc/mediatek/mt8183/dramc_pi_cal... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/#/c/32243/3/src/soc/mediatek/mt8183/dramc_pi_cal... PS3, Line 35: -16
why is this changed, and will this be a problem for other existing DRAM modules? […]
From the calibration log of EMCP-SAMSUNG DDR, we found the begin pass range of RX window early than other DDR. Because the pass window will be affected by SOC chip manufacturing process, DDR chip manufacturing process, current volatge, temperature and some other environment. If we not increase the begin scan range, the pass window maybe get wrong result at some board.
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32243 )
Change subject: mediatek/mt8183: add SAMSUNG and MICRON EMCP LPDDR4X support ......................................................................
Patch Set 3:
(4 comments)
https://review.coreboot.org/#/c/32243/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32243/3//COMMIT_MSG@7 PS3, Line 7: support remove the trailing 'support'
https://review.coreboot.org/#/c/32243/3//COMMIT_MSG@7 PS3, Line 7: add support
https://review.coreboot.org/#/c/32243/3//COMMIT_MSG@9 PS3, Line 9: add change 'add something support' to 'support something'.
https://review.coreboot.org/#/c/32243/3//COMMIT_MSG@11 PS3, Line 11: Add a comment here to explain why the DQS is also changed, for example:
Also changed DQS starting offset to increase the scan range for RX window, which is required for Samsung EMCP DDR, and should not impact other existing memory modules.
Hello Julius Werner, You-Cheng Syu, Tristan Hsieh, Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32243
to look at the new patch set (#4).
Change subject: mediatek/mt8183: support SAMSUNG and MICRON EMCP LPDDR4X DDR bootup ......................................................................
mediatek/mt8183: support SAMSUNG and MICRON EMCP LPDDR4X DDR bootup
support SAMSUNG KMDP6001DA-B425 EMCP LPDDR4X DDR supprot MICRON MT29VZZZAD8DQKSL EMCP LPDDR4X DDR
from the calibration log of MICRON MT29VZZZAD8DQKSL, we found the begin pass range of RX window early than other DDR type. change the DQS starting offset to increase the scan range of RX window.
BUG=b:80501386 BRANCH=none TEST=Boots correctly on EMCP DRAM
Change-Id: I5fcc8673a2fbd7ec3a8776ab61c57f8903ddda20 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/mainboard/google/kukui/sdram_configs.c M src/mainboard/google/kukui/sdram_params/Makefile.inc A src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c A src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c 5 files changed, 87 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/32243/4
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32243 )
Change subject: mediatek/mt8183: support SAMSUNG and MICRON EMCP LPDDR4X DDR bootup ......................................................................
Patch Set 4: Code-Review+1
(3 comments)
just some nits.
https://review.coreboot.org/#/c/32243/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32243/4//COMMIT_MSG@9 PS4, Line 9: support Support
https://review.coreboot.org/#/c/32243/4//COMMIT_MSG@10 PS4, Line 10: supprot Support
https://review.coreboot.org/#/c/32243/4//COMMIT_MSG@12 PS4, Line 12: from From
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32243 )
Change subject: mediatek/mt8183: support SAMSUNG and MICRON EMCP LPDDR4X DDR bootup ......................................................................
Patch Set 4:
(5 comments)
https://review.coreboot.org/#/c/32243/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32243/4//COMMIT_MSG@13 PS4, Line 13: than other than with other
https://review.coreboot.org/#/c/32243/4//COMMIT_MSG@13 PS4, Line 13: begin start of
https://review.coreboot.org/#/c/32243/4//COMMIT_MSG@13 PS4, Line 13: early earlier
https://review.coreboot.org/#/c/32243/4//COMMIT_MSG@12 PS4, Line 12: from the calibration log of MICRON MT29VZZZAD8DQKSL, we found : the begin pass range of RX window early than other DDR type. Why is that a bad thing? Is that contradicting some specification?
https://review.coreboot.org/#/c/32243/4//COMMIT_MSG@14 PS4, Line 14: change Change
Hello Julius Werner, You-Cheng Syu, Tristan Hsieh, Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32243
to look at the new patch set (#5).
Change subject: mediatek/mt8183: support SAMSUNG and MICRON EMCP LPDDR4X DDR bootup ......................................................................
mediatek/mt8183: support SAMSUNG and MICRON EMCP LPDDR4X DDR bootup
Support SAMSUNG KMDP6001DA-B425 EMCP LPDDR4X DDR Supprot MICRON MT29VZZZAD8DQKSL EMCP LPDDR4X DDR
From the calibration log of MICRON MT29VZZZAD8DQKSL, we found the begin pass range of RX window early than other DDR type. So need change the DQS starting offset to increase the scan range of RX window.
BAUG=b:80501386 BRANCH=none TEST=Boots correctly on EMCP DRAM
Change-Id: I5fcc8673a2fbd7ec3a8776ab61c57f8903ddda20 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/mainboard/google/kukui/sdram_configs.c M src/mainboard/google/kukui/sdram_params/Makefile.inc A src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c A src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c 5 files changed, 87 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/32243/5
Hello Julius Werner, You-Cheng Syu, Tristan Hsieh, Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32243
to look at the new patch set (#6).
Change subject: mediatek/mt8183: support SAMSUNG and MICRON EMCP LPDDR4X DDR bootup ......................................................................
mediatek/mt8183: support SAMSUNG and MICRON EMCP LPDDR4X DDR bootup
Support SAMSUNG KMDP6001DA-B425 EMCP LPDDR4X DDR Supprot MICRON MT29VZZZAD8DQKSL EMCP LPDDR4X DDR
From the calibration log of MICRON MT29VZZZAD8DQKSL, we found the begin pass range of RX window earlier than with other DDR type. So need change the DQS starting offset to increase the scan range of RX window.
BAUG=b:80501386 BRANCH=none TEST=Boots correctly on EMCP DRAM
Change-Id: I5fcc8673a2fbd7ec3a8776ab61c57f8903ddda20 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/mainboard/google/kukui/sdram_configs.c M src/mainboard/google/kukui/sdram_params/Makefile.inc A src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c A src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c 5 files changed, 87 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/32243/6
huayang duan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32243 )
Change subject: mediatek/mt8183: support SAMSUNG and MICRON EMCP LPDDR4X DDR bootup ......................................................................
Patch Set 6:
(8 comments)
https://review.coreboot.org/#/c/32243/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32243/4//COMMIT_MSG@9 PS4, Line 9: support
Support
Done
https://review.coreboot.org/#/c/32243/4//COMMIT_MSG@10 PS4, Line 10: supprot
Support
Done
https://review.coreboot.org/#/c/32243/4//COMMIT_MSG@12 PS4, Line 12: from
From
Done
https://review.coreboot.org/#/c/32243/4//COMMIT_MSG@13 PS4, Line 13: early
earlier
Done
https://review.coreboot.org/#/c/32243/4//COMMIT_MSG@13 PS4, Line 13: than other
than with other
Done
https://review.coreboot.org/#/c/32243/4//COMMIT_MSG@12 PS4, Line 12: from the calibration log of MICRON MT29VZZZAD8DQKSL, we found : the begin pass range of RX window early than other DDR type.
Why is that a bad thing? Is that contradicting some specification?
The delay begin is just used to scan the QQ to QDS window, not relate with bad thing. For normal case, we should put the delay begin to very very left side and do window scan to found the left pass window. Then delay+1 do window scan again, repeat do those step to found all pass window. The value of very very left side should be -63 for first bring-up, because it can cover all case. But it will spend more time to scan QQ to QDS window. after bring-up success, we will analyze the QQ to QDS window scan UART logs, decrease the unused scan to reduce the bootup time, so we change the delay begin from -63 to -10. But From the calibration log of EMCP-SAMSUNG DDR, we found the begin pass range of RX window early than other DDR. Because the pass window will be affected by SOC chip manufacturing process, DDR chip manufacturing process, current volatge, temperature and some other environment. If we not increase the begin scan range, the pass window maybe get wrong result at some board.
https://review.coreboot.org/#/c/32243/4//COMMIT_MSG@13 PS4, Line 13: begin
start of
we prefer using begin for DRAM calibration flow
https://review.coreboot.org/#/c/32243/4//COMMIT_MSG@14 PS4, Line 14: change
Change
Done
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32243 )
Change subject: mediatek/mt8183: support SAMSUNG and MICRON EMCP LPDDR4X DDR bootup ......................................................................
Patch Set 6: Code-Review+1
(2 comments)
https://review.coreboot.org/#/c/32243/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32243/6//COMMIT_MSG@9 PS6, Line 9: Support SAMSUNG KMDP6001DA-B425 EMCP LPDDR4X DDR : Supprot MICRON MT29VZZZAD8DQKSL EMCP LPDDR4X DDR Format this as a list/enumeration.
https://review.coreboot.org/#/c/32243/6//COMMIT_MSG@10 PS6, Line 10: Supprot Support
Hello Julius Werner, You-Cheng Syu, Paul Menzel, Tristan Hsieh, Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32243
to look at the new patch set (#7).
Change subject: mediatek/mt8183: support SAMSUNG and MICRON EMCP LPDDR4X DDR bootup ......................................................................
mediatek/mt8183: support SAMSUNG and MICRON EMCP LPDDR4X DDR bootup
Support SAMSUNG KMDP6001DA-B425 and MICRON MT29VZZZAD8DQKSL EMCP LPDDR4X DDR
From the calibration log of MICRON MT29VZZZAD8DQKSL, we found the begin pass range of RX window earlier than with other DDR type. So need change the DQS starting offset to increase the scan range of RX window.
BAUG=b:80501386 BRANCH=none TEST=Boots correctly on EMCP DRAM
Change-Id: I5fcc8673a2fbd7ec3a8776ab61c57f8903ddda20 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/mainboard/google/kukui/sdram_configs.c M src/mainboard/google/kukui/sdram_params/Makefile.inc A src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c A src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c 5 files changed, 87 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/32243/7
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32243 )
Change subject: mediatek/mt8183: support SAMSUNG and MICRON EMCP LPDDR4X DDR bootup ......................................................................
Patch Set 8: Code-Review+1
You-Cheng Syu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32243 )
Change subject: mediatek/mt8183: support SAMSUNG and MICRON EMCP LPDDR4X DDR bootup ......................................................................
Patch Set 8: Code-Review+1
(1 comment)
https://review.coreboot.org/#/c/32243/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32243/8//COMMIT_MSG@15 PS8, Line 15: BAUG BUG
Hello Julius Werner, You-Cheng Syu, Paul Menzel, Tristan Hsieh, Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32243
to look at the new patch set (#9).
Change subject: mediatek/mt8183: support SAMSUNG and MICRON EMCP LPDDR4X DDR bootup ......................................................................
mediatek/mt8183: support SAMSUNG and MICRON EMCP LPDDR4X DDR bootup
Support SAMSUNG KMDP6001DA-B425 and MICRON MT29VZZZAD8DQKSL EMCP LPDDR4X DDR
From the calibration log of MICRON MT29VZZZAD8DQKSL, we found the begin pass range of RX window earlier than with other DDR type. So need change the DQS starting offset to increase the scan range of RX window.
BUG=b:80501386 BRANCH=none TEST=Boots correctly on EMCP DRAM
Change-Id: I5fcc8673a2fbd7ec3a8776ab61c57f8903ddda20 Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/mainboard/google/kukui/sdram_configs.c M src/mainboard/google/kukui/sdram_params/Makefile.inc A src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c A src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c 5 files changed, 87 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/32243/9
huayang duan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32243 )
Change subject: mediatek/mt8183: support SAMSUNG and MICRON EMCP LPDDR4X DDR bootup ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/#/c/32243/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32243/8//COMMIT_MSG@15 PS8, Line 15: BAUG
BUG
Done
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32243 )
Change subject: mediatek/mt8183: support SAMSUNG and MICRON EMCP LPDDR4X DDR bootup ......................................................................
Patch Set 9: Code-Review+1
@jwerner do you want to take a final review?
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32243 )
Change subject: mediatek/mt8183: support SAMSUNG and MICRON EMCP LPDDR4X DDR bootup ......................................................................
Patch Set 9: Code-Review+2
Huayang Duan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32243 )
Change subject: mediatek/mt8183: support SAMSUNG and MICRON EMCP LPDDR4X DDR bootup ......................................................................
Patch Set 9: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32243 )
Change subject: mediatek/mt8183: support SAMSUNG and MICRON EMCP LPDDR4X DDR bootup ......................................................................
mediatek/mt8183: support SAMSUNG and MICRON EMCP LPDDR4X DDR bootup
Support SAMSUNG KMDP6001DA-B425 and MICRON MT29VZZZAD8DQKSL EMCP LPDDR4X DDR
From the calibration log of MICRON MT29VZZZAD8DQKSL, we found the begin pass range of RX window earlier than with other DDR type. So need change the DQS starting offset to increase the scan range of RX window.
BUG=b:80501386 BRANCH=none TEST=Boots correctly on EMCP DRAM
Change-Id: I5fcc8673a2fbd7ec3a8776ab61c57f8903ddda20 Signed-off-by: Huayang Duan huayang.duan@mediatek.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/32243 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Hung-Te Lin hungte@chromium.org Reviewed-by: Julius Werner jwerner@chromium.org Reviewed-by: Huayang Duan huayang.duan@mediatek.corp-partner.google.com --- M src/mainboard/google/kukui/sdram_configs.c M src/mainboard/google/kukui/sdram_params/Makefile.inc A src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c A src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c 5 files changed, 87 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Hung-Te Lin: Looks good to me, but someone else must approve Huayang Duan: Looks good to me, approved
diff --git a/src/mainboard/google/kukui/sdram_configs.c b/src/mainboard/google/kukui/sdram_configs.c index cbfb08d..5931c79 100644 --- a/src/mainboard/google/kukui/sdram_configs.c +++ b/src/mainboard/google/kukui/sdram_configs.c @@ -21,6 +21,8 @@ static const char *const sdram_configs[] = { [1] = "sdram-lpddr4x-H9HCNNNCPMALHR-4GB", [2] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB", + [3] = "sdram-lpddr4x-KMDP6001DA-B425-4GB", + [5] = "sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB", };
static struct sdram_params params; diff --git a/src/mainboard/google/kukui/sdram_params/Makefile.inc b/src/mainboard/google/kukui/sdram_params/Makefile.inc index 1e11140..77158a5 100644 --- a/src/mainboard/google/kukui/sdram_params/Makefile.inc +++ b/src/mainboard/google/kukui/sdram_params/Makefile.inc @@ -1,6 +1,8 @@ sdram-params := sdram-params += sdram-lpddr4x-H9HCNNNCPMALHR-4GB sdram-params += sdram-lpddr4x-MT53E1G32D4NQ-4GB +sdram-params += sdram-lpddr4x-KMDP6001DA-B425-4GB +sdram-params += sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB
$(foreach params,$(sdram-params), \ $(eval cbfs-files-y += $(params)) \ diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c new file mode 100644 index 0000000..1e0c362 --- /dev/null +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/emi.h> + +struct sdram_params params = { + .impedance = { + [ODT_OFF] = {0x9, 0x7, 0x0, 0xF}, + [ODT_ON] = {0xA, 0x9, 0x0, 0xE} + }, + .wr_level = { + [CHANNEL_A] = { {0x21, 0x21}, {0x20, 0x20} }, + [CHANNEL_B] = { {0x1E, 0x1F}, {0x1D, 0x1E} } + }, + .cbt_cs = { + [CHANNEL_A] = {0x1, 0x1}, + [CHANNEL_B] = {0x2, 0x2} + }, + .cbt_mr12 = { + [CHANNEL_A] = {0x56, 0x56}, + [CHANNEL_B] = {0x58, 0x5C} + }, + .emi_cona_val = 0xF053F154, + .emi_conh_val = 0x44440003, + .emi_conf_val = 0x00421000, + .chn_emi_cona_val = {0x0444F051, 0x0444F051}, + .cbt_mode_extern = CBT_NORMAL_MODE, + .delay_cell_unit = 868, +}; diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c new file mode 100644 index 0000000..512023b --- /dev/null +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/emi.h> + +struct sdram_params params = { + .impedance = { + [ODT_OFF] = {0x9, 0x7, 0x0, 0xF}, + [ODT_ON] = {0xA, 0x9, 0x0, 0xE} + }, + .wr_level = { + [CHANNEL_A] = { {0x21, 0x21}, {0x20, 0x20} }, + [CHANNEL_B] = { {0x21, 0x28}, {0x21, 0x29} } + }, + .cbt_cs = { + [CHANNEL_A] = {0x2, 0x2}, + [CHANNEL_B] = {0x2, 0x2} + }, + .cbt_mr12 = { + [CHANNEL_A] = {0x5E, 0x5E}, + [CHANNEL_B] = {0x5E, 0x5C} + }, + .emi_cona_val = 0xF053F154, + .emi_conh_val = 0x44440003, + .emi_conf_val = 0x00421000, + .chn_emi_cona_val = {0x0444F051, 0x0444F051}, + .cbt_mode_extern = CBT_NORMAL_MODE, + .delay_cell_unit = 868, +}; diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index 6dc8fa6..05f793e 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -32,7 +32,7 @@
enum { FIRST_DQ_DELAY = 0, - FIRST_DQS_DELAY = -10, + FIRST_DQS_DELAY = -16, MAX_DQDLY_TAPS = 16, MAX_RX_DQDLY_TAPS = 63, };
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Huayang Duan (Code Review) -
huayang duan (Code Review)
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Hung-Te Lin (Code Review)
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Julius Werner (Code Review)
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Patrick Georgi (Code Review)
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Paul Menzel (Code Review)
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You-Cheng Syu (Code Review)