Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38341 )
Change subject: soc/intel/tigerlake: Update PCI dev denifition ......................................................................
soc/intel/tigerlake: Update PCI dev denifition
Update pci dev defintion according to TGL EDS Add GSPI3 case in chip.c
Reference Process EDS#575681 rev1.0 PCH EDS#576591 rev1.2
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I4717ac3cc877b13978b18ada504740512f10c709 --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/include/soc/pci_devs.h 2 files changed, 37 insertions(+), 44 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/38341/1
diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index 95be276..8b0bec0 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -105,6 +105,7 @@ case PCH_DEVFN_GSPI0: return "SPI0"; case PCH_DEVFN_GSPI1: return "SPI1"; case PCH_DEVFN_GSPI2: return "SPI2"; + case PCH_DEVFN_GSPI3: return "SPI3"; /* Keeping ACPI device name coherent with ec.asl */ case PCH_DEVFN_ESPI: return "LPCB"; case PCH_DEVFN_P2SB: return "P2SB"; diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h index f54ab4b..432e1ea 100644 --- a/src/soc/intel/tigerlake/include/soc/pci_devs.h +++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h @@ -39,32 +39,54 @@ #define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) #define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0)
-#define SA_DEV_SLOT_DSP 0x04 -#define SA_DEVFN_DSP PCI_DEVFN(SA_DEV_SLOT_DSP, 0) -#define SA_DEV_DSP PCI_DEV(0, SA_DEV_SLOT_DSP, 0) +#define SA_DEV_SLOT_DPTF 0x04 +#define SA_DEVFN_DPTF PCI_DEVFN(SA_DEV_SLOT_DPTF, 0) +#define SA_DEV_DPTF PCI_DEV(0, SA_DEV_SLOT_DPTF, 0)
/* PCH Devices */ -#define PCH_DEV_SLOT_THERMAL 0x12 -#define PCH_DEVFN_THERMAL _PCH_DEVFN(THERMAL, 0) -#define PCH_DEVFN_UFS _PCH_DEVFN(THERMAL, 5) -#define PCH_DEVFN_GSPI2 _PCH_DEVFN(THERMAL, 6) -#define PCH_DEV_THERMAL _PCH_DEV(THERMAL, 0) -#define PCH_DEV_UFS _PCH_DEV(THERMAL, 5) -#define PCH_DEV_GSPI2 _PCH_DEV(THERMAL, 6) +#define PCH_DEV_SLOT_TBT 0x07 +#define PCH_DEVFN_TBT0 _PCH_DEVFN(TBT, 0) +#define PCH_DEVFN_TBT1 _PCH_DEVFN(TBT, 1) +#define PCH_DEVFN_TBT2 _PCH_DEVFN(TBT, 2) +#define PCH_DEVFN_TBT3 _PCH_DEVFN(TBT, 3) +#define PCH_DEV_TBT0 _PCH_DEV(TBT, 0) +#define PCH_DEV_TBT1 _PCH_DEV(TBT, 1) +#define PCH_DEV_TBT2 _PCH_DEV(TBT, 2) +#define PCH_DEV_TBT3 _PCH_DEV(TBT, 3)
-#define PCH_DEV_SLOT_ISH 0x13 +#define PCH_DEV_SLOT_SIO4 0x10 +#define PCH_DEVFN_CNVI_BT _PCH_DEVFN(SIO4, 2) +#define PCH_DEVFN_THC0 _PCH_DEVFN(SIO4, 6) +#define PCH_DEVFN_THC1 _PCH_DEVFN(SIO4, 7) +#define PCH_DEV_CNVI_BT _PCH_DEV(SIO4, 2) +#define PCH_DEV_THC0 _PCH_DEV(SIO4, 6) +#define PCH_DEV_THC1 _PCH_DEV(SIO4, 7) + +#define PCH_DEV_SLOT_SIO5 0x11 +#define PCH_DEVFN_UART3 _PCH_DEVFN(SIO5, 0) +#define PCH_DEV_UART3 _PCH_DEVFN(SIO5, 0) + +#define PCH_DEV_SLOT_ISH 0x12 #define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0) +#define PCH_DEVFN_THERMAL _PCH_DEVFN(ISH, 1) +#define PCH_DEVFN_GSPI2 _PCH_DEVFN(ISH, 6) #define PCH_DEV_ISH _PCH_DEV(ISH, 0) +#define PCH_DEV_THERMAL _PCH_DEV(ISH, 1) +#define PCH_DEV_GSPI2 _PCH_DEV(ISH, 6) + +#define PCH_DEV_SLOT_SIO6 0x13 +#define PCH_DEVFN_GSPI3 _PCH_DEVFN(SIO6, 0) +#define PCH_DEV_GSPI3 _PCH_DEV(SIO6, 0)
#define PCH_DEV_SLOT_XHCI 0x14 #define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0) #define PCH_DEVFN_USBOTG _PCH_DEVFN(XHCI, 1) +#define PCH_DEVFN_SRAM _PCH_DEVFN(XHCI, 2) #define PCH_DEVFN_CNViWIFI _PCH_DEVFN(XHCI, 3) -#define PCH_DEVFN_SDCARD _PCH_DEVFN(XHCI, 5) #define PCH_DEV_XHCI _PCH_DEV(XHCI, 0) #define PCH_DEV_USBOTG _PCH_DEV(XHCI, 1) +#define PCH_DEV_SRAM _PCH_DEV(XHCI, 2) #define PCH_DEV_CNViWIFI _PCH_DEV(XHCI, 3) -#define PCH_DEV_SDCARD _PCH_DEV(XHCI, 5)
#define PCH_DEV_SLOT_SIO1 0x15 #define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO1, 0) @@ -102,10 +124,6 @@ #define PCH_DEV_I2C5 _PCH_DEV(SIO2, 1) #define PCH_DEV_UART2 _PCH_DEV(SIO2, 2)
-#define PCH_DEV_SLOT_STORAGE 0x1A -#define PCH_DEVFN_EMMC _PCH_DEVFN(STORAGE, 0) -#define PCH_DEV_EMMC _PCH_DEV(STORAGE, 0) - #define PCH_DEV_SLOT_PCIE 0x1c #define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE, 0) #define PCH_DEVFN_PCIE2 _PCH_DEVFN(PCIE, 1) @@ -129,36 +147,10 @@ #define PCH_DEVFN_PCIE10 _PCH_DEVFN(PCIE_1, 1) #define PCH_DEVFN_PCIE11 _PCH_DEVFN(PCIE_1, 2) #define PCH_DEVFN_PCIE12 _PCH_DEVFN(PCIE_1, 3) -#define PCH_DEVFN_PCIE13 _PCH_DEVFN(PCIE_1, 4) -#define PCH_DEVFN_PCIE14 _PCH_DEVFN(PCIE_1, 5) -#define PCH_DEVFN_PCIE15 _PCH_DEVFN(PCIE_1, 6) -#define PCH_DEVFN_PCIE16 _PCH_DEVFN(PCIE_1, 7) #define PCH_DEV_PCIE9 _PCH_DEV(PCIE_1, 0) #define PCH_DEV_PCIE10 _PCH_DEV(PCIE_1, 1) #define PCH_DEV_PCIE11 _PCH_DEV(PCIE_1, 2) #define PCH_DEV_PCIE12 _PCH_DEV(PCIE_1, 3) -#define PCH_DEV_PCIE13 _PCH_DEV(PCIE_1, 4) -#define PCH_DEV_PCIE14 _PCH_DEV(PCIE_1, 5) -#define PCH_DEV_PCIE15 _PCH_DEV(PCIE_1, 6) -#define PCH_DEV_PCIE16 _PCH_DEV(PCIE_1, 7) - -#define PCH_DEV_SLOT_PCIE_2 0x1b -#define PCH_DEVFN_PCIE17 _PCH_DEVFN(PCIE_2, 0) -#define PCH_DEVFN_PCIE18 _PCH_DEVFN(PCIE_2, 1) -#define PCH_DEVFN_PCIE19 _PCH_DEVFN(PCIE_2, 2) -#define PCH_DEVFN_PCIE20 _PCH_DEVFN(PCIE_2, 3) -#define PCH_DEVFN_PCIE21 _PCH_DEVFN(PCIE_2, 4) -#define PCH_DEVFN_PCIE22 _PCH_DEVFN(PCIE_2, 5) -#define PCH_DEVFN_PCIE23 _PCH_DEVFN(PCIE_2, 6) -#define PCH_DEVFN_PCIE24 _PCH_DEVFN(PCIE_2, 7) -#define PCH_DEV_PCIE17 _PCH_DEV(PCIE_2, 0) -#define PCH_DEV_PCIE18 _PCH_DEV(PCIE_2, 1) -#define PCH_DEV_PCIE19 _PCH_DEV(PCIE_2, 2) -#define PCH_DEV_PCIE20 _PCH_DEV(PCIE_2, 3) -#define PCH_DEV_PCIE21 _PCH_DEV(PCIE_2, 4) -#define PCH_DEV_PCIE22 _PCH_DEV(PCIE_2, 5) -#define PCH_DEV_PCIE23 _PCH_DEV(PCIE_2, 6) -#define PCH_DEV_PCIE24 _PCH_DEV(PCIE_2, 7)
#define PCH_DEV_SLOT_SIO3 0x1e #define PCH_DEVFN_UART0 _PCH_DEVFN(SIO3, 0) @@ -180,7 +172,7 @@ #define PCH_DEVFN_SPI _PCH_DEVFN(ESPI, 5) #define PCH_DEVFN_GBE _PCH_DEVFN(ESPI, 6) #define PCH_DEVFN_TRACEHUB _PCH_DEVFN(ESPI, 7) -#define PCH_DEV_ESPI _PCH_DEV(ESPI, 0) +#define PCH_DEV_ESPI _PCH_DEV(ESPI, 0) #define PCH_DEV_LPC PCH_DEV_ESPI #define PCH_DEV_P2SB _PCH_DEV(ESPI, 1)
Hello Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38341
to look at the new patch set (#2).
Change subject: soc/intel/tigerlake: update pci dev definition ......................................................................
soc/intel/tigerlake: update pci dev definition
Update pci dev definition according to TGL EDS Add GSPI3 case in chip.c
Reference TGL Process EDS#575681 rev1.0 TGL PCH EDS#576591 rev1.2
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I4717ac3cc877b13978b18ada504740512f10c709 --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/include/soc/pci_devs.h 2 files changed, 37 insertions(+), 44 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/38341/2
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38341 )
Change subject: soc/intel/tigerlake: update pci dev definition ......................................................................
Patch Set 2: Code-Review+1
Hello Patrick Rudolph, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38341
to look at the new patch set (#3).
Change subject: soc/intel/tigerlake: update pci dev definition ......................................................................
soc/intel/tigerlake: update pci dev definition
Update pci dev definition according to TGL EDS Add GSPI3 case in chip.c
Reference TGL Process EDS#575681 rev1.0 TGL PCH EDS#576591 rev1.2
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I4717ac3cc877b13978b18ada504740512f10c709 --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/include/soc/pci_devs.h 2 files changed, 37 insertions(+), 44 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/38341/3
Hello Patrick Rudolph, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38341
to look at the new patch set (#4).
Change subject: soc/intel/tigerlake: update pci dev definition ......................................................................
soc/intel/tigerlake: update pci dev definition
Update pci dev definition according to TGL EDS Add GSPI3 case in chip.c
Reference TGL Process EDS#575681 rev1.0 TGL PCH EDS#576591 rev1.2
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I4717ac3cc877b13978b18ada504740512f10c709 --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/include/soc/pci_devs.h 2 files changed, 37 insertions(+), 44 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/38341/4
Hello Patrick Rudolph, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38341
to look at the new patch set (#5).
Change subject: soc/intel/tigerlake: update pci dev definition ......................................................................
soc/intel/tigerlake: update pci dev definition
Update pci dev definition according to TGL EDS Add GSPI3 case in chip.c
Reference TGL Process EDS#575681 rev1.0 TGL PCH EDS#576591 rev1.2
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I4717ac3cc877b13978b18ada504740512f10c709 --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/include/soc/pci_devs.h 2 files changed, 37 insertions(+), 44 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/38341/5
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38341 )
Change subject: soc/intel/tigerlake: update pci dev definition ......................................................................
Patch Set 5: Code-Review+1
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38341 )
Change subject: soc/intel/tigerlake: update pci dev definition ......................................................................
Patch Set 5: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38341 )
Change subject: soc/intel/tigerlake: update pci dev definition ......................................................................
Patch Set 5:
(14 comments)
https://review.coreboot.org/c/coreboot/+/38341/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38341/5//COMMIT_MSG@7 PS5, Line 7: u nit: Update
https://review.coreboot.org/c/coreboot/+/38341/5//COMMIT_MSG@9 PS5, Line 9: Update nit: This change updates
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.c:
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/chi... PS5, Line 54: case 9: return "HS10"; acpi/xhci.asl lists upto HS12 devices, but there are only devices upto HS10 here.
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/chi... PS5, Line 63: case 3: return "SS04"; acpi/xhci.asl lists upto SS06 devices, but there are only devices upto SS04 here.
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/chi... PS5, Line 72: devfn I see a number of devices that do not have their corresponding device in any .asl file. Shouldn't the .asl files be updated as well?
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/chi... PS5, Line 74: GFX0 Shouldn't there be a corresponding device in .asl file somewhere?
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/chi... PS5, Line 75: ISHB same here.
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/chi... PS5, Line 108: case PCH_DEVFN_GSPI3: return "SPI3"; I believe this device should be added to serialio.asl as well.
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/chi... PS5, Line 116: IGBE Shouldn't this be GLAN as per pch_glan.asl
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/inc... PS5, Line 47: PCH_DEV_SLOT_TBT I don't think this is a PCH device.
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/inc... PS5, Line 57: SIO4 It doesn't matter much technically. But I believe SIO4 here refers to Serial I/O 4. Shouldn't this be numbered in order i.e. SIO1 here and then continue with SIO2 and so on.
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/inc... PS5, Line 71: #define PCH_DEVFN_THERMAL _PCH_DEVFN(ISH, 1) I don't see this in the EDS.
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/inc... PS5, Line 85: iWIFI I think it would be better to keep this as CNVI_WIFI just like CNVI_BT done above in line 61.
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/inc... PS5, Line 89: PCH_DEV_CNViWIFI same here.
Hello Srinidhi N Kaushik, Patrick Rudolph, Subrata Banik, Nick Vaccaro, caveh jalali, Shaunak Saha, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38341
to look at the new patch set (#6).
Change subject: soc/intel/tigerlake: update pci dev definition ......................................................................
soc/intel/tigerlake: update pci dev definition
Update pci dev definition according to TGL EDS Add GSPI3 case in chip.c
Reference TGL Process EDS#575681 rev1.0 TGL PCH EDS#576591 rev1.2
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I4717ac3cc877b13978b18ada504740512f10c709 --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/finalize.c M src/soc/intel/tigerlake/include/soc/pci_devs.h 3 files changed, 40 insertions(+), 56 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/38341/6
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38341 )
Change subject: soc/intel/tigerlake: update pci dev definition ......................................................................
Patch Set 6:
(9 comments)
https://review.coreboot.org/c/coreboot/+/38341/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38341/5//COMMIT_MSG@7 PS5, Line 7: u
nit: Update
Ack
https://review.coreboot.org/c/coreboot/+/38341/5//COMMIT_MSG@9 PS5, Line 9: Update
nit: This change updates
Ack
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.c:
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/chi... PS5, Line 108: case PCH_DEVFN_GSPI3: return "SPI3";
I believe this device should be added to serialio.asl as well.
Yes, it's in serialio.asl : https://review.coreboot.org/c/coreboot/+/37781/18/src/soc/intel/tigerlake/ac...
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/chi... PS5, Line 116: IGBE
Shouldn't this be GLAN as per pch_glan. […]
Ack
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/inc... PS5, Line 47: PCH_DEV_SLOT_TBT
I don't think this is a PCH device.
Ack
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/inc... PS5, Line 57: SIO4
It doesn't matter much technically. But I believe SIO4 here refers to Serial I/O 4. […]
This is based on or order of Device id(0x10, 0x11, etc)
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/inc... PS5, Line 71: #define PCH_DEVFN_THERMAL _PCH_DEVFN(ISH, 1)
I don't see this in the EDS.
It just added dummy number(unused device) for avoid compile failure and it'll not be used in finalize.c Compile failure happen because this is used in SOC_INTEL_COMMON_BLOCK_THERMAL code and SOC_INTEL_COMMON_BLOCK_THERMAL is selected in SOC_INTEL_COMMON_PCH_BASE. We're trying to find better way to clean this.
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/inc... PS5, Line 85: iWIFI
I think it would be better to keep this as CNVI_WIFI just like CNVI_BT done above in line 61.
Ack
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/inc... PS5, Line 89: PCH_DEV_CNViWIFI
same here.
Ack
Hello Srinidhi N Kaushik, Patrick Rudolph, Subrata Banik, Nick Vaccaro, caveh jalali, Shaunak Saha, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38341
to look at the new patch set (#7).
Change subject: soc/intel/tigerlake: Update pci dev definition ......................................................................
soc/intel/tigerlake: Update pci dev definition
This change updates pci dev definition according to TGL EDS Add GSPI3 case in chip.c according to update pci dev definitions
Reference TGL Process EDS#575681 rev1.0 TGL PCH EDS#576591 rev1.2
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I4717ac3cc877b13978b18ada504740512f10c709 --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/finalize.c M src/soc/intel/tigerlake/include/soc/pci_devs.h 3 files changed, 40 insertions(+), 56 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/38341/7
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38341 )
Change subject: soc/intel/tigerlake: Update pci dev definition ......................................................................
Patch Set 7:
(8 comments)
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.c:
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/chi... PS5, Line 54: case 9: return "HS10";
acpi/xhci.asl lists upto HS12 devices, but there are only devices upto HS10 here.
No update here? I don't expect to see any changes for this clubbed into this same CL. This is just something that I noticed and I think should be addressed somewhere (probably in a separate CL).
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/chi... PS5, Line 63: case 3: return "SS04";
acpi/xhci.asl lists upto SS06 devices, but there are only devices upto SS04 here.
No update here?
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/chi... PS5, Line 72: devfn
I see a number of devices that do not have their corresponding device in any .asl file. […]
No update here?
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/chi... PS5, Line 74: GFX0
Shouldn't there be a corresponding device in . […]
No update here?
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/chi... PS5, Line 75: ISHB
same here.
No update here?
https://review.coreboot.org/c/coreboot/+/38341/7/src/soc/intel/tigerlake/fin... File src/soc/intel/tigerlake/finalize.c:
https://review.coreboot.org/c/coreboot/+/38341/7/src/soc/intel/tigerlake/fin... PS7, Line 78: pch_thermal_configuration(); Why was this removed? This seems totally unrelated?
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/inc... PS5, Line 57: SIO4
This is based on or order of Device id(0x10, 0x11, etc)
I understand the order of device id, but shouldn't this be SIO0, and 0x11 SIO1 and so on?
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/inc... PS5, Line 71: #define PCH_DEVFN_THERMAL _PCH_DEVFN(ISH, 1)
It just added dummy number(unused device) for avoid compile failure and it'll not be used in finaliz […]
Where is it being tracked? At minimum, there should be a comment indicating why this is being put in.
Is it really difficult to just remove the SOC_INTEL_COMMON_BLOCK_THERMAL selection from SOC_INTEL_COMMON_PCH_BASE and move it to individual SoCs that really have this block?
BTW, does TGL not have this block altogether?
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38341 )
Change subject: soc/intel/tigerlake: Update pci dev definition ......................................................................
Patch Set 7:
(9 comments)
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.c:
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/chi... PS5, Line 54: case 9: return "HS10";
No update here? I don't expect to see any changes for this clubbed into this same CL. […]
This will be updated https://review.coreboot.org/c/coreboot/+/37781
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/chi... PS5, Line 63: case 3: return "SS04";
No update here?
This will be updated https://review.coreboot.org/c/coreboot/+/37781
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/chi... PS5, Line 72: devfn
No update here?
We have minimum ASL file in Coreboot, not all these return have coresponding asl and we'll add need base. We'll check and clean up if TGL doesn't use it in ASL file. Update will be done in https://review.coreboot.org/c/coreboot/+/37783
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/chi... PS5, Line 74: GFX0
No update here?
Not used in TGL ASL, delete in https://review.coreboot.org/c/coreboot/+/37783
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/chi... PS5, Line 75: ISHB
No update here?
Not used in TGL ASL, delete in https://review.coreboot.org/c/coreboot/+/37783
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/chi... PS5, Line 116: IGBE
Ack
Will update in https://review.coreboot.org/c/coreboot/+/37783
https://review.coreboot.org/c/coreboot/+/38341/7/src/soc/intel/tigerlake/fin... File src/soc/intel/tigerlake/finalize.c:
https://review.coreboot.org/c/coreboot/+/38341/7/src/soc/intel/tigerlake/fin... PS7, Line 78: pch_thermal_configuration();
Why was this removed? This seems totally unrelated?
This function is INTEL_COMMON_BLOCK_THERMAL code.
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/inc... PS5, Line 57: SIO4
I understand the order of device id, but shouldn't this be SIO0, and 0x11 SIO1 and so on?
Will update naming
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/inc... PS5, Line 71: #define PCH_DEVFN_THERMAL _PCH_DEVFN(ISH, 1)
Where is it being tracked? At minimum, there should be a comment indicating why this is being put in […]
We're discussing internally, we'll have patch for fixing this issue. TGL doesn't have issue with dummy definition as TGL does not use INTEL_COMMON_BLOCK_THERMAL code.
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38341 )
Change subject: soc/intel/tigerlake: Update pci dev definition ......................................................................
Patch Set 7:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.c:
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/chi... PS5, Line 74: GFX0
Not used in TGL ASL, delete in https://review.coreboot. […]
Ack
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/chi... PS5, Line 75: ISHB
Not used in TGL ASL, delete in https://review.coreboot. […]
Ack
https://review.coreboot.org/c/coreboot/+/38341/7/src/soc/intel/tigerlake/fin... File src/soc/intel/tigerlake/finalize.c:
https://review.coreboot.org/c/coreboot/+/38341/7/src/soc/intel/tigerlake/fin... PS7, Line 78: pch_thermal_configuration();
This function is INTEL_COMMON_BLOCK_THERMAL code.
Resolve compile issue by https://review.coreboot.org/c/coreboot/+/38444/2/src/soc/intel/skylake/final... So, revert this change
Hello Srinidhi N Kaushik, Patrick Rudolph, Subrata Banik, Nick Vaccaro, Caveh Jalali, build bot (Jenkins), Shaunak Saha, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38341
to look at the new patch set (#8).
Change subject: soc/intel/tigerlake: Update pci dev definition ......................................................................
soc/intel/tigerlake: Update pci dev definition
This change updates pci dev definition according to TGL EDS Add GSPI3 case in chip.c according to update pci dev definitions
Reference TGL Process EDS#575681 rev1.0 TGL PCH EDS#576591 rev1.2
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I4717ac3cc877b13978b18ada504740512f10c709 --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/include/soc/pci_devs.h 2 files changed, 40 insertions(+), 47 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/38341/8
Hello Srinidhi N Kaushik, Patrick Rudolph, Subrata Banik, Nick Vaccaro, Caveh Jalali, build bot (Jenkins), Shaunak Saha, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38341
to look at the new patch set (#9).
Change subject: soc/intel/tigerlake: Update pci dev definition ......................................................................
soc/intel/tigerlake: Update pci dev definition
This change updates pci dev definition according to TGL EDS Add GSPI3 case in chip.c according to update pci dev definitions
Reference TGL Process EDS#575681 rev1.0 TGL PCH EDS#576591 rev1.2
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I4717ac3cc877b13978b18ada504740512f10c709 --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/include/soc/pci_devs.h 2 files changed, 62 insertions(+), 71 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/38341/9
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38341 )
Change subject: soc/intel/tigerlake: Update pci dev definition ......................................................................
Patch Set 9: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/inc... PS5, Line 57: SIO4
Will update naming
Done
https://review.coreboot.org/c/coreboot/+/38341/5/src/soc/intel/tigerlake/inc... PS5, Line 71: #define PCH_DEVFN_THERMAL _PCH_DEVFN(ISH, 1)
We're discussing internally, we'll have patch for fixing this issue. […]
official patch for fixing build issue is done by https://review.coreboot.org/c/coreboot/+/38444 Delete
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38341 )
Change subject: soc/intel/tigerlake: Update pci dev definition ......................................................................
Patch Set 9: Code-Review+1
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38341 )
Change subject: soc/intel/tigerlake: Update pci dev definition ......................................................................
Patch Set 9:
(4 comments)
https://review.coreboot.org/c/coreboot/+/38341/9//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38341/9//COMMIT_MSG@9 PS9, Line 9: This change updates pci dev definition according to TGL EDS Dot/period at the end of sentences please.
https://review.coreboot.org/c/coreboot/+/38341/9//COMMIT_MSG@10 PS9, Line 10: Add GSPI3 case in chip.c according to update pci dev definitions Ditto.
https://review.coreboot.org/c/coreboot/+/38341/9//COMMIT_MSG@10 PS9, Line 10: update updated
https://review.coreboot.org/c/coreboot/+/38341/9/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/38341/9/src/soc/intel/tigerlake/inc... PS9, Line 54: #define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3) Align with tabs?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38341 )
Change subject: soc/intel/tigerlake: Update pci dev definition ......................................................................
Patch Set 9: Code-Review+1
LGTM after comments from Paul are addressed.
Hello Srinidhi N Kaushik, Patrick Rudolph, Subrata Banik, Nick Vaccaro, Caveh Jalali, build bot (Jenkins), Shaunak Saha, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38341
to look at the new patch set (#10).
Change subject: soc/intel/tigerlake: Update pci dev definition ......................................................................
soc/intel/tigerlake: Update pci dev definition
This change updates pci dev definition according to TGL EDS. Add GSPI3 case in chip.c according to updated pci dev definitions.
Reference TGL Process EDS#575681 rev1.0 TGL PCH EDS#576591 rev1.2
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I4717ac3cc877b13978b18ada504740512f10c709 --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/include/soc/pci_devs.h 2 files changed, 62 insertions(+), 71 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/38341/10
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38341 )
Change subject: soc/intel/tigerlake: Update pci dev definition ......................................................................
Patch Set 10:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38341/9//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38341/9//COMMIT_MSG@9 PS9, Line 9: This change updates pci dev definition according to TGL EDS
Dot/period at the end of sentences please.
Ack
https://review.coreboot.org/c/coreboot/+/38341/9//COMMIT_MSG@10 PS9, Line 10: update
updated
Ack
https://review.coreboot.org/c/coreboot/+/38341/9//COMMIT_MSG@10 PS9, Line 10: Add GSPI3 case in chip.c according to update pci dev definitions
Ditto.
Ack
Hello Srinidhi N Kaushik, Patrick Rudolph, Subrata Banik, Nick Vaccaro, Caveh Jalali, build bot (Jenkins), Shaunak Saha, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38341
to look at the new patch set (#11).
Change subject: soc/intel/tigerlake: Update pci dev definition ......................................................................
soc/intel/tigerlake: Update pci dev definition
This change updates pci dev definition according to TGL EDS. Add GSPI3 case in chip.c according to updated pci dev definitions.
Reference TGL Process EDS#575681 rev1.0 TGL PCH EDS#576591 rev1.2
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I4717ac3cc877b13978b18ada504740512f10c709 --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/include/soc/pci_devs.h 2 files changed, 62 insertions(+), 71 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/38341/11
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38341 )
Change subject: soc/intel/tigerlake: Update pci dev definition ......................................................................
Patch Set 11: Code-Review+1
Rebase code based on updated dependent patch(https://review.coreboot.org/c/coreboot/+/37783)
Hello Srinidhi N Kaushik, Patrick Rudolph, Subrata Banik, Nick Vaccaro, Caveh Jalali, build bot (Jenkins), Shaunak Saha, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38341
to look at the new patch set (#12).
Change subject: soc/intel/tigerlake: Update pci dev definition ......................................................................
soc/intel/tigerlake: Update pci dev definition
This change updates pci dev definition according to TGL EDS. Add GSPI3 case in chip.c according to updated pci dev definitions.
Reference TGL Process EDS#575681 rev1.0 TGL PCH EDS#576591 rev1.2
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I4717ac3cc877b13978b18ada504740512f10c709 --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/include/soc/pci_devs.h 2 files changed, 62 insertions(+), 71 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/38341/12
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38341 )
Change subject: soc/intel/tigerlake: Update pci dev definition ......................................................................
Patch Set 12: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/38341/9/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/38341/9/src/soc/intel/tigerlake/inc... PS9, Line 54: #define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3)
Align with tabs?
Ack
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38341 )
Change subject: soc/intel/tigerlake: Update pci dev definition ......................................................................
Patch Set 12: Code-Review+2
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38341 )
Change subject: soc/intel/tigerlake: Update pci dev definition ......................................................................
Patch Set 12: Code-Review+2
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38341 )
Change subject: soc/intel/tigerlake: Update pci dev definition ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38341/12/src/soc/intel/tigerlake/in... File src/soc/intel/tigerlake/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/38341/12/src/soc/intel/tigerlake/in... PS12, Line 105: #define PCH_DEV_SLOT_STORAGE 0x1A Why is this getting removed? Atleast as per Jasperlake EDS, EMMC is present on this PCH Device ID and I believe Jasperlake is going to share this PCI BDF definition with TGL.
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38341 )
Change subject: soc/intel/tigerlake: Update pci dev definition ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38341/12/src/soc/intel/tigerlake/in... File src/soc/intel/tigerlake/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/38341/12/src/soc/intel/tigerlake/in... PS12, Line 105: #define PCH_DEV_SLOT_STORAGE 0x1A
Why is this getting removed? Atleast as per Jasperlake EDS, EMMC is present on this PCH Device ID an […]
This path will clean up based on TGL and JSL will use separate patch to update all JSL change
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38341 )
Change subject: soc/intel/tigerlake: Update pci dev definition ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38341/12/src/soc/intel/tigerlake/in... File src/soc/intel/tigerlake/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/38341/12/src/soc/intel/tigerlake/in... PS12, Line 105: #define PCH_DEV_SLOT_STORAGE 0x1A
This path will clean up based on TGL and JSL will use separate patch to update all JSL change
Done
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38341 )
Change subject: soc/intel/tigerlake: Update pci dev definition ......................................................................
soc/intel/tigerlake: Update pci dev definition
This change updates pci dev definition according to TGL EDS. Add GSPI3 case in chip.c according to updated pci dev definitions.
Reference TGL Process EDS#575681 rev1.0 TGL PCH EDS#576591 rev1.2
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I4717ac3cc877b13978b18ada504740512f10c709 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38341 Reviewed-by: Nick Vaccaro nvaccaro@google.com Reviewed-by: Subrata Banik subrata.banik@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/include/soc/pci_devs.h 2 files changed, 62 insertions(+), 71 deletions(-)
Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Nick Vaccaro: Looks good to me, approved Wonkyu Kim: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index 2637cf8..6f6e153 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -97,6 +97,7 @@ case PCH_DEVFN_GSPI0: return "SPI0"; case PCH_DEVFN_GSPI1: return "SPI1"; case PCH_DEVFN_GSPI2: return "SPI2"; + case PCH_DEVFN_GSPI3: return "SPI3"; /* Keeping ACPI device name coherent with ec.asl */ case PCH_DEVFN_ESPI: return "LPCB"; case PCH_DEVFN_HDA: return "HDAS"; diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h index f54ab4b..9a35e73 100644 --- a/src/soc/intel/tigerlake/include/soc/pci_devs.h +++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h @@ -39,42 +39,62 @@ #define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) #define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0)
-#define SA_DEV_SLOT_DSP 0x04 -#define SA_DEVFN_DSP PCI_DEVFN(SA_DEV_SLOT_DSP, 0) -#define SA_DEV_DSP PCI_DEV(0, SA_DEV_SLOT_DSP, 0) +#define SA_DEV_SLOT_DPTF 0x04 +#define SA_DEVFN_DPTF PCI_DEVFN(SA_DEV_SLOT_DPTF, 0) +#define SA_DEV_DPTF PCI_DEV(0, SA_DEV_SLOT_DPTF, 0) + +#define SA_DEV_SLOT_TBT 0x07 +#define SA_DEVFN_TBT0 PCI_DEVFN(SA_DEV_SLOT_TBT, 0) +#define SA_DEVFN_TBT1 PCI_DEVFN(SA_DEV_SLOT_TBT, 1) +#define SA_DEVFN_TBT2 PCI_DEVFN(SA_DEV_SLOT_TBT, 2) +#define SA_DEVFN_TBT3 PCI_DEVFN(SA_DEV_SLOT_TBT, 3) +#define SA_DEV_TBT0 PCI_DEV(0, SA_DEV_SLOT_TBT, 0) +#define SA_DEV_TBT1 PCI_DEV(0, SA_DEV_SLOT_TBT, 1) +#define SA_DEV_TBT2 PCI_DEV(0, SA_DEV_SLOT_TBT, 2) +#define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3)
/* PCH Devices */ -#define PCH_DEV_SLOT_THERMAL 0x12 -#define PCH_DEVFN_THERMAL _PCH_DEVFN(THERMAL, 0) -#define PCH_DEVFN_UFS _PCH_DEVFN(THERMAL, 5) -#define PCH_DEVFN_GSPI2 _PCH_DEVFN(THERMAL, 6) -#define PCH_DEV_THERMAL _PCH_DEV(THERMAL, 0) -#define PCH_DEV_UFS _PCH_DEV(THERMAL, 5) -#define PCH_DEV_GSPI2 _PCH_DEV(THERMAL, 6) +#define PCH_DEV_SLOT_SIO0 0x10 +#define PCH_DEVFN_CNVI_BT _PCH_DEVFN(SIO0, 2) +#define PCH_DEVFN_THC0 _PCH_DEVFN(SIO0, 6) +#define PCH_DEVFN_THC1 _PCH_DEVFN(SIO0, 7) +#define PCH_DEV_CNVI_BT _PCH_DEV(SIO0, 2) +#define PCH_DEV_THC0 _PCH_DEV(SIO0, 6) +#define PCH_DEV_THC1 _PCH_DEV(SIO0, 7)
-#define PCH_DEV_SLOT_ISH 0x13 +#define PCH_DEV_SLOT_SIO1 0x11 +#define PCH_DEVFN_UART3 _PCH_DEVFN(SIO1, 0) +#define PCH_DEV_UART3 _PCH_DEVFN(SIO1, 0) + +#define PCH_DEV_SLOT_ISH 0x12 #define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0) +#define PCH_DEVFN_GSPI2 _PCH_DEVFN(ISH, 6) #define PCH_DEV_ISH _PCH_DEV(ISH, 0) +#define PCH_DEV_GSPI2 _PCH_DEV(ISH, 6) + +#define PCH_DEV_SLOT_SIO2 0x13 +#define PCH_DEVFN_GSPI3 _PCH_DEVFN(SIO2, 0) +#define PCH_DEV_GSPI3 _PCH_DEV(SIO2, 0)
#define PCH_DEV_SLOT_XHCI 0x14 #define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0) #define PCH_DEVFN_USBOTG _PCH_DEVFN(XHCI, 1) -#define PCH_DEVFN_CNViWIFI _PCH_DEVFN(XHCI, 3) -#define PCH_DEVFN_SDCARD _PCH_DEVFN(XHCI, 5) +#define PCH_DEVFN_SRAM _PCH_DEVFN(XHCI, 2) +#define PCH_DEVFN_CNVI_WIFI _PCH_DEVFN(XHCI, 3) #define PCH_DEV_XHCI _PCH_DEV(XHCI, 0) #define PCH_DEV_USBOTG _PCH_DEV(XHCI, 1) -#define PCH_DEV_CNViWIFI _PCH_DEV(XHCI, 3) -#define PCH_DEV_SDCARD _PCH_DEV(XHCI, 5) +#define PCH_DEV_SRAM _PCH_DEV(XHCI, 2) +#define PCH_DEV_CNVI_WIFI _PCH_DEV(XHCI, 3)
-#define PCH_DEV_SLOT_SIO1 0x15 -#define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO1, 0) -#define PCH_DEVFN_I2C1 _PCH_DEVFN(SIO1, 1) -#define PCH_DEVFN_I2C2 _PCH_DEVFN(SIO1, 2) -#define PCH_DEVFN_I2C3 _PCH_DEVFN(SIO1, 3) -#define PCH_DEV_I2C0 _PCH_DEV(SIO1, 0) -#define PCH_DEV_I2C1 _PCH_DEV(SIO1, 1) -#define PCH_DEV_I2C2 _PCH_DEV(SIO1, 2) -#define PCH_DEV_I2C3 _PCH_DEV(SIO1, 3) +#define PCH_DEV_SLOT_SIO3 0x15 +#define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO3, 0) +#define PCH_DEVFN_I2C1 _PCH_DEVFN(SIO3, 1) +#define PCH_DEVFN_I2C2 _PCH_DEVFN(SIO3, 2) +#define PCH_DEVFN_I2C3 _PCH_DEVFN(SIO3, 3) +#define PCH_DEV_I2C0 _PCH_DEV(SIO3, 0) +#define PCH_DEV_I2C1 _PCH_DEV(SIO3, 1) +#define PCH_DEV_I2C2 _PCH_DEV(SIO3, 2) +#define PCH_DEV_I2C3 _PCH_DEV(SIO3, 3)
#define PCH_DEV_SLOT_CSE 0x16 #define PCH_DEVFN_CSE _PCH_DEVFN(CSE, 0) @@ -94,17 +114,13 @@ #define PCH_DEVFN_SATA _PCH_DEVFN(SATA, 0) #define PCH_DEV_SATA _PCH_DEV(SATA, 0)
-#define PCH_DEV_SLOT_SIO2 0x19 -#define PCH_DEVFN_I2C4 _PCH_DEVFN(SIO2, 0) -#define PCH_DEVFN_I2C5 _PCH_DEVFN(SIO2, 1) -#define PCH_DEVFN_UART2 _PCH_DEVFN(SIO2, 2) -#define PCH_DEV_I2C4 _PCH_DEV(SIO2, 0) -#define PCH_DEV_I2C5 _PCH_DEV(SIO2, 1) -#define PCH_DEV_UART2 _PCH_DEV(SIO2, 2) - -#define PCH_DEV_SLOT_STORAGE 0x1A -#define PCH_DEVFN_EMMC _PCH_DEVFN(STORAGE, 0) -#define PCH_DEV_EMMC _PCH_DEV(STORAGE, 0) +#define PCH_DEV_SLOT_SIO4 0x19 +#define PCH_DEVFN_I2C4 _PCH_DEVFN(SIO4, 0) +#define PCH_DEVFN_I2C5 _PCH_DEVFN(SIO4, 1) +#define PCH_DEVFN_UART2 _PCH_DEVFN(SIO4, 2) +#define PCH_DEV_I2C4 _PCH_DEV(SIO4, 0) +#define PCH_DEV_I2C5 _PCH_DEV(SIO4, 1) +#define PCH_DEV_UART2 _PCH_DEV(SIO4, 2)
#define PCH_DEV_SLOT_PCIE 0x1c #define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE, 0) @@ -129,46 +145,20 @@ #define PCH_DEVFN_PCIE10 _PCH_DEVFN(PCIE_1, 1) #define PCH_DEVFN_PCIE11 _PCH_DEVFN(PCIE_1, 2) #define PCH_DEVFN_PCIE12 _PCH_DEVFN(PCIE_1, 3) -#define PCH_DEVFN_PCIE13 _PCH_DEVFN(PCIE_1, 4) -#define PCH_DEVFN_PCIE14 _PCH_DEVFN(PCIE_1, 5) -#define PCH_DEVFN_PCIE15 _PCH_DEVFN(PCIE_1, 6) -#define PCH_DEVFN_PCIE16 _PCH_DEVFN(PCIE_1, 7) #define PCH_DEV_PCIE9 _PCH_DEV(PCIE_1, 0) #define PCH_DEV_PCIE10 _PCH_DEV(PCIE_1, 1) #define PCH_DEV_PCIE11 _PCH_DEV(PCIE_1, 2) #define PCH_DEV_PCIE12 _PCH_DEV(PCIE_1, 3) -#define PCH_DEV_PCIE13 _PCH_DEV(PCIE_1, 4) -#define PCH_DEV_PCIE14 _PCH_DEV(PCIE_1, 5) -#define PCH_DEV_PCIE15 _PCH_DEV(PCIE_1, 6) -#define PCH_DEV_PCIE16 _PCH_DEV(PCIE_1, 7)
-#define PCH_DEV_SLOT_PCIE_2 0x1b -#define PCH_DEVFN_PCIE17 _PCH_DEVFN(PCIE_2, 0) -#define PCH_DEVFN_PCIE18 _PCH_DEVFN(PCIE_2, 1) -#define PCH_DEVFN_PCIE19 _PCH_DEVFN(PCIE_2, 2) -#define PCH_DEVFN_PCIE20 _PCH_DEVFN(PCIE_2, 3) -#define PCH_DEVFN_PCIE21 _PCH_DEVFN(PCIE_2, 4) -#define PCH_DEVFN_PCIE22 _PCH_DEVFN(PCIE_2, 5) -#define PCH_DEVFN_PCIE23 _PCH_DEVFN(PCIE_2, 6) -#define PCH_DEVFN_PCIE24 _PCH_DEVFN(PCIE_2, 7) -#define PCH_DEV_PCIE17 _PCH_DEV(PCIE_2, 0) -#define PCH_DEV_PCIE18 _PCH_DEV(PCIE_2, 1) -#define PCH_DEV_PCIE19 _PCH_DEV(PCIE_2, 2) -#define PCH_DEV_PCIE20 _PCH_DEV(PCIE_2, 3) -#define PCH_DEV_PCIE21 _PCH_DEV(PCIE_2, 4) -#define PCH_DEV_PCIE22 _PCH_DEV(PCIE_2, 5) -#define PCH_DEV_PCIE23 _PCH_DEV(PCIE_2, 6) -#define PCH_DEV_PCIE24 _PCH_DEV(PCIE_2, 7) - -#define PCH_DEV_SLOT_SIO3 0x1e -#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO3, 0) -#define PCH_DEVFN_UART1 _PCH_DEVFN(SIO3, 1) -#define PCH_DEVFN_GSPI0 _PCH_DEVFN(SIO3, 2) -#define PCH_DEVFN_GSPI1 _PCH_DEVFN(SIO3, 3) -#define PCH_DEV_UART0 _PCH_DEV(SIO3, 0) -#define PCH_DEV_UART1 _PCH_DEV(SIO3, 1) -#define PCH_DEV_GSPI0 _PCH_DEV(SIO3, 2) -#define PCH_DEV_GSPI1 _PCH_DEV(SIO3, 3) +#define PCH_DEV_SLOT_SIO5 0x1e +#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO5, 0) +#define PCH_DEVFN_UART1 _PCH_DEVFN(SIO5, 1) +#define PCH_DEVFN_GSPI0 _PCH_DEVFN(SIO5, 2) +#define PCH_DEVFN_GSPI1 _PCH_DEVFN(SIO5, 3) +#define PCH_DEV_UART0 _PCH_DEV(SIO5, 0) +#define PCH_DEV_UART1 _PCH_DEV(SIO5, 1) +#define PCH_DEV_GSPI0 _PCH_DEV(SIO5, 2) +#define PCH_DEV_GSPI1 _PCH_DEV(SIO5, 3)
#define PCH_DEV_SLOT_ESPI 0x1f #define PCH_DEV_SLOT_LPC PCH_DEV_SLOT_ESPI @@ -180,7 +170,7 @@ #define PCH_DEVFN_SPI _PCH_DEVFN(ESPI, 5) #define PCH_DEVFN_GBE _PCH_DEVFN(ESPI, 6) #define PCH_DEVFN_TRACEHUB _PCH_DEVFN(ESPI, 7) -#define PCH_DEV_ESPI _PCH_DEV(ESPI, 0) +#define PCH_DEV_ESPI _PCH_DEV(ESPI, 0) #define PCH_DEV_LPC PCH_DEV_ESPI #define PCH_DEV_P2SB _PCH_DEV(ESPI, 1)
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Furquan Shaikh (Code Review) -
Karthik Ramasubramanian (Code Review)
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Nick Vaccaro (Code Review)
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Patrick Georgi (Code Review)
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Paul Menzel (Code Review)
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Subrata Banik (Code Review)
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Wonkyu Kim (Code Review)