Jérémy Compostella has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86587?usp=email )
Change subject: treewide: Rename PM4LE -> PML4E ......................................................................
treewide: Rename PM4LE -> PML4E
The x86 (AMD and Intel) spec defines it as Page-Map Level-4 Entry. It is annoying when searching for the wrong abbreviation in the spec so fix it everywhere it occurs.
source: Intel 64 spec April 2022 and AMD64 spec April 2024.
Signed-off-by: Maximilian Brune maximilian.brune@9elements.com Change-Id: I730235beea69b3720f080bbade083c2eeed26587 Reviewed-on: https://review.coreboot.org/c/coreboot/+/86587 Reviewed-by: Jérémy Compostella jeremy.compostella@intel.com Reviewed-by: Patrick Rudolph patrick.rudolph@9elements.com Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Benjamin Doron benjamin.doron00@gmail.com Reviewed-by: Andy Ebrahiem ahmet.ebrahiem@9elements.com --- M payloads/libpayload/arch/x86/head_64.S M payloads/libpayload/arch/x86/pt.S M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/x86/64bit/mode_switch2.S M src/cpu/x86/64bit/pt.S M src/cpu/x86/64bit/pt1G.S M src/cpu/x86/smm/smm_module_loader.c M src/soc/amd/common/block/cpu/noncar/pre_c.S M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S 12 files changed, 22 insertions(+), 22 deletions(-)
Approvals: Jérémy Compostella: Looks good to me, approved Angel Pons: Looks good to me, approved Patrick Rudolph: Looks good to me, approved Andy Ebrahiem: Looks good to me, but someone else must approve Benjamin Doron: Looks good to me, approved build bot (Jenkins): Verified
diff --git a/payloads/libpayload/arch/x86/head_64.S b/payloads/libpayload/arch/x86/head_64.S index 6524274..1fd0d01 100644 --- a/payloads/libpayload/arch/x86/head_64.S +++ b/payloads/libpayload/arch/x86/head_64.S @@ -70,7 +70,7 @@ movl %eax, cb_header_ptr
call init_page_table - movl $pm4le, %eax + movl $pml4e, %eax
/* load identity mapped page tables */ movl %eax, %cr3 @@ -107,7 +107,7 @@ movq %rdi, cb_header_ptr
call init_page_table - movq $pm4le, %rax + movq $pml4e, %rax
/* load identity mapped page tables */ movq %rax, %cr3 diff --git a/payloads/libpayload/arch/x86/pt.S b/payloads/libpayload/arch/x86/pt.S index 0e6e7bf..080d044 100644 --- a/payloads/libpayload/arch/x86/pt.S +++ b/payloads/libpayload/arch/x86/pt.S @@ -41,10 +41,10 @@ #define _D (1ULL << 6) #define _PS (1ULL << 7)
-.section .bss.pm4le -.global pm4le +.section .bss.pml4e +.global pml4e .align 4096 -pm4le: +pml4e: .skip 8
.section .bss.main_page_table @@ -144,6 +144,6 @@
leave: or $(_PRES + _RW + _US + _A), %eax - mov %eax, pm4le + mov %eax, pml4e
ret diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 227ddf4..de945a9 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -163,7 +163,7 @@ subl $4, %esp
#if ENV_X86_64 - setup_longmode $PM4LE + setup_longmode $PML4E
movd %mm2, %rdi shlq $32, %rdi diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 9485cd4..7186422 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -214,7 +214,7 @@ andl $0xfffffff0, %esp
#if ENV_X86_64 - setup_longmode $PM4LE + setup_longmode $PML4E
movd %mm2, %rdi shlq $32, %rdi diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 1cb422d..1843954 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -363,7 +363,7 @@ subl $4, %esp
#if ENV_X86_64 - setup_longmode $PM4LE + setup_longmode $PML4E
movd %mm2, %rdi shlq $32, %rdi /* BIST */ diff --git a/src/cpu/x86/64bit/mode_switch2.S b/src/cpu/x86/64bit/mode_switch2.S index 18c6425..3be56c4 100644 --- a/src/cpu/x86/64bit/mode_switch2.S +++ b/src/cpu/x86/64bit/mode_switch2.S @@ -21,7 +21,7 @@ mov %esp, %ebp
/* Enter long mode, preserves ebx */ - setup_longmode $PM4LE + setup_longmode $PML4E
/* Align stack */ movabs $0xfffffffffffffff0, %rax diff --git a/src/cpu/x86/64bit/pt.S b/src/cpu/x86/64bit/pt.S index 4b2f3c8..1297296 100644 --- a/src/cpu/x86/64bit/pt.S +++ b/src/cpu/x86/64bit/pt.S @@ -17,9 +17,9 @@ #define _GEN_DIR(a) (_PRES + _RW + _US + _A + (a)) #define _GEN_PAGE(a) (_PRES + _RW + _US + _PS + _A + _D + (a))
-.global PM4LE +.global PML4E .align 4096 -PM4LE: +PML4E: .quad _GEN_DIR(PDPT)
.align 4096 diff --git a/src/cpu/x86/64bit/pt1G.S b/src/cpu/x86/64bit/pt1G.S index 3502964..42cdfb1 100644 --- a/src/cpu/x86/64bit/pt1G.S +++ b/src/cpu/x86/64bit/pt1G.S @@ -17,9 +17,9 @@ #define _GEN_DIR(a) (_PRES + _RW + _US + _A + (a)) #define _GEN_PAGE(a) (_PRES + _RW + _US + _PS + _A + _D + (a))
-.global PM4LE +.global PML4E .align 4096 -PM4LE: +PML4E: .quad _GEN_DIR(PDPT)
.align 4096 diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index c6d0753..ba92e1ff 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -420,27 +420,27 @@ #define _GEN_PAGE(a) (_PRES + _RW + _US + _PS + _A + _D + (a)) #define PAGE_SIZE 8
-/* Return the PM4LE */ +/* Return the PML4E */ static uintptr_t install_page_table(const uintptr_t handler_base) { const bool one_g_pages = !!(cpuid_edx(0x80000001) & (1 << 26)); /* 4 1G pages or 4 PDPE entries with 512 * 2M pages */ const size_t pages_needed = one_g_pages ? 4 : 2048 + 4; const uintptr_t pages_base = ALIGN_DOWN(handler_base - pages_needed * PAGE_SIZE, 4096); - const uintptr_t pm4le = ALIGN_DOWN(pages_base - 8, 4096); + const uintptr_t pml4e = ALIGN_DOWN(pages_base - 8, 4096);
if (one_g_pages) { for (size_t i = 0; i < 4; i++) write64p(pages_base + i * PAGE_SIZE, _GEN_PAGE(1ull * GiB * i)); - write64p(pm4le, _GEN_DIR(pages_base)); + write64p(pml4e, _GEN_DIR(pages_base)); } else { for (size_t i = 0; i < 2048; i++) write64p(pages_base + i * PAGE_SIZE, _GEN_PAGE(2ull * MiB * i)); - write64p(pm4le, _GEN_DIR(pages_base + 2048 * PAGE_SIZE)); + write64p(pml4e, _GEN_DIR(pages_base + 2048 * PAGE_SIZE)); for (size_t i = 0; i < 4; i++) write64p(pages_base + (2048 + i) * PAGE_SIZE, _GEN_DIR(pages_base + 4096 * i)); } - return pm4le; + return pml4e; }
/* diff --git a/src/soc/amd/common/block/cpu/noncar/pre_c.S b/src/soc/amd/common/block/cpu/noncar/pre_c.S index 0e0be52..b754588 100644 --- a/src/soc/amd/common/block/cpu/noncar/pre_c.S +++ b/src/soc/amd/common/block/cpu/noncar/pre_c.S @@ -28,7 +28,7 @@ post_code(POSTCODE_BOOTBLOCK_PRE_C_ENTRY)
#if ENV_X86_64 - setup_longmode $PM4LE + setup_longmode $PML4E #endif
/* Clear .bss section */ diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 2c4beeb..b84a06e 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -280,7 +280,7 @@ andl $0xfffffff0, %esp
#if ENV_X86_64 - setup_longmode $PM4LE + setup_longmode $PML4E
movd %mm2, %rdi shlq $32, %rdi diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 4e057f0..ed735db 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -83,7 +83,7 @@ movl %ecx, temp_memory_start
#if ENV_X86_64 - setup_longmode $PM4LE + setup_longmode $PML4E movl %ebp, %edi shlq $32, %rdi movd %mm1, %rsi
-
Jérémy Compostella (Code Review)