Change in coreboot[master]: soc/amd/picasso: Update southbridge

[Marshall Dawson (Code Review)]

Hello Richard Spiegel, build bot (Jenkins), Martin Roth, Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/33770

to look at the new patch set (#14).

Change subject: soc/amd/picasso: Update southbridge
......................................................................

soc/amd/picasso: Update southbridge

Picasso's FCH has many similarities to Stoney Ridge, so few changes
are necessary.  The most notable changes are:
 * Update the index values for the C00/C01 interrupt routing
 * FORCE_STPCLK_RETRY is not present
 * PCIB is not defined
 * FCH MISC Registers 0xfed80e00 numbering has changed
 * C-state base moves from PM register to MSR

Signed-off-by: Marshall Dawson 
Change-Id: I69dfc4a875006639aa330385680d150331840e40
---
M src/soc/amd/picasso/include/soc/amd_pci_int_defs.h
M src/soc/amd/picasso/include/soc/cpu.h
M src/soc/amd/picasso/include/soc/southbridge.h
M src/soc/amd/picasso/smihandler.c
M src/soc/amd/picasso/southbridge.c
5 files changed, 104 insertions(+), 166 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/33770/14