Change in ...coreboot[master]: mb/intel/icelake_rvp: Add DPTF information

[Sumeet R Pawnikar (Code Review)]

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29804

Change subject: mb/intel/icelake_rvp: Add DPTF information
......................................................................

mb/intel/icelake_rvp: Add DPTF information

Currently, using these placeholder values. These will be
updated after thermal tuning.

Change-Id: Id206417e2e8029abe1de2a35f58dc4e801f3986b
Signed-off-by: Sumeet Pawnikar 
---
A src/mainboard/intel/icelake_rvp/acpi/dptf.asl
M src/mainboard/intel/icelake_rvp/dsdt.asl
2 files changed, 47 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/29804/1

diff --git a/src/mainboard/intel/icelake_rvp/acpi/dptf.asl b/src/mainboard/intel/icelake_rvp/acpi/dptf.asl
new file mode 100644
index 0000000..cbe0792
--- /dev/null
+++ b/src/mainboard/intel/icelake_rvp/acpi/dptf.asl
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE	80
+#define DPTF_CPU_CRITICAL	99
+
+Name (DTRT, Package () {
+	/* CPU Throttle Effect on CPU */
+	Package () { _SB.PCI0.B0D4, _SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+	0x2,		/* Revision */
+	Package () {	/* Power Limit 1 */
+		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
+		1600,	/* PowerLimitMinimum */
+		15000,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		200	/* StepSize */
+	},
+	Package () {	/* Power Limit 2 */
+		1,	/* PowerLimitIndex, 1 for Power Limit 2 */
+		8000,	/* PowerLimitMinimum */
+		8000,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		1000	/* StepSize */
+	}
+})
diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl
index 7951501..2cc4079 100644
--- a/src/mainboard/intel/icelake_rvp/dsdt.asl
+++ b/src/mainboard/intel/icelake_rvp/dsdt.asl
@@ -33,7 +33,11 @@
    	{
    		#include <soc/intel/icelake/acpi/northbridge.asl>
    		#include <soc/intel/icelake/acpi/southbridge.asl>
+
    	}
+
+		// Dynamic Platform Thermal Framework
+		#include "acpi/dptf.asl"
    }

#if IS_ENABLED(CONFIG_CHROMEOS)