[S] Change in coreboot[main]: mb/google/nissa/var/anraggar: Config TCSS AUX according board_id

[Weimin Wu (Code Review)]

Weimin Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80259?usp=email )

Change subject: mb/google/nissa/var/anraggar: Config TCSS AUX according board_id
......................................................................

mb/google/nissa/var/anraggar: Config TCSS AUX according board_id

EVT mini build (board_id = 2) change retimer IC.
Need to reconfigure TCSS AUX connect to SOC directly.
Perform compatibility processing based on board_id.

BUG=b:none
TEST=DP function of MB and DB workable

Change-Id: I53974ec7444912a63d0fe0a9303c9e5d6941f68d
Signed-off-by: Weimin Wu 
---
M src/mainboard/google/brya/variants/anraggar/overridetree.cb
M src/mainboard/google/brya/variants/anraggar/variant.c
2 files changed, 34 insertions(+), 15 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/80259/1

diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb
index 9646f29..bc4f8e5 100644
--- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb
+++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb
@@ -60,21 +60,6 @@
    # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
    register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515"

-	# SOC Aux orientation override:
-	# This is a bitfield that corresponds to up to 4 TCSS ports.
-	# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
-	# TcssAuxOri = 0100b
-	# Bit0 set to "0" indicates has retimer on USBC Port0, on the DB.
-	# Bit2 set to "1" indicates no retimer on USBC Port1, on the MB.
-	# Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
-	# motherboard to USBC connector
-	register "tcss_aux_ori" = "4"
-
-	register "typec_aux_bias_pads[0]" = "{
-		.pad_auxp_dc = GPP_E22,
-		.pad_auxn_dc = GPP_E23
-	}"
-
    # FIVR configurations for anraggar are disabled since the board doesn't have V1p05 and Vnn
    # bypass rails implemented.
    register "ext_fivr_settings" = "{
diff --git a/src/mainboard/google/brya/variants/anraggar/variant.c b/src/mainboard/google/brya/variants/anraggar/variant.c
index 4221a5b..486e7f3 100644
--- a/src/mainboard/google/brya/variants/anraggar/variant.c
+++ b/src/mainboard/google/brya/variants/anraggar/variant.c
@@ -1,5 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

+#include <chip.h>
+#include <soc/gpio_soc_defs.h>
+#include <baseboard/variants.h>
+#include <boardid.h>
 #include <fw_config.h>
 #include <sar.h>

@@ -7,3 +11,33 @@
 {
    return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI));
 }
+
+void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
+{
+	/*
+	* SOC Aux orientation override:
+	* This is a bitfield that corresponds to up to 4 TCSS ports.
+	* Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
+	* Bit0, Bit2 set to "0" indicates has retimer on TCSS Port.
+	* Bit0, Bit2 set to "1" indicates no retimer on TCSS Port.
+	* Bit1, Bit3 set to "0" indicates Aux lines are not swapped on TCSS Port.
+	* Bit1, Bit3 set to "1" indicates Aux lines are swapped on TCSS Port.
+	*/
+
+	switch (board_id()){
+	case 0:	/* proto */
+	case 1:	/* evt */
+		config->tcss_aux_ori = 4;
+		config->typec_aux_bias_pads[1].pad_auxp_dc = GPP_E22;
+		config->typec_aux_bias_pads[1].pad_auxn_dc = GPP_E23;
+		break;
+	case 2:	/* evt mini build (DB TCSS AUX connect to SOC directly) */
+		config->tcss_aux_ori = 5;
+		config->typec_aux_bias_pads[1].pad_auxp_dc = GPP_E22;
+		config->typec_aux_bias_pads[1].pad_auxn_dc = GPP_E23;
+		config->typec_aux_bias_pads[0].pad_auxp_dc = GPP_A19;
+		config->typec_aux_bias_pads[0].pad_auxn_dc = GPP_A20;
+		break;
+	default:
+	}
+}