Patch set updated for coreboot: x86 chipsets: Link non-code flow CHIPSET_BOOTBLOCK_INCLUDE files
Alexandru Gagniuc (mr.nuke.me@gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11856
-gerrit
commit 91892b662a7fe11dc92e60eaeb9479bcd4ddefc8 Author: Alexandru Gagniuc mr.nuke.me@gmail.com Date: Mon Oct 5 08:00:51 2015 -0700
x86 chipsets: Link non-code flow CHIPSET_BOOTBLOCK_INCLUDE files
Non-code flow assembly stubs do not have to be included in bootblock.S, now that we have more freedom in bootblock linking. Rather than bringing these stubs to the config system, just link them in the bootblock.
Note that we cannot fully remove CHIPSET_BOOTBLOCK_INCLUDE at this point, as some intel SOCs use this stub for code flow.
objdump -h build/cbfs/fallback/bootblock.debug on a few random boards confirms that the appropriate sections are still included in the final binary.
Change-Id: Id3f9ece14e399c1cc83090f407780c4a05a076f0 Signed-off-by: Alexandru Gagniuc mr.nuke.me@gmail.com --- src/cpu/dmp/vortex86ex/Kconfig | 4 - src/cpu/dmp/vortex86ex/Makefile.inc | 2 + src/cpu/dmp/vortex86ex/biosdata.S | 80 +++++++++++++ src/cpu/dmp/vortex86ex/biosdata.inc | 80 ------------- src/cpu/dmp/vortex86ex/biosdata_ex.S | 172 +++++++++++++++++++++++++++ src/cpu/dmp/vortex86ex/biosdata_ex.inc | 172 --------------------------- src/cpu/dmp/vortex86ex/chipset_bootblock.inc | 2 - src/northbridge/via/vx800/Kconfig | 8 -- src/northbridge/via/vx800/Makefile.inc | 1 + src/northbridge/via/vx800/romstrap.S | 47 ++++++++ src/northbridge/via/vx800/romstrap.inc | 47 -------- src/northbridge/via/vx900/Kconfig | 4 - src/northbridge/via/vx900/Makefile.inc | 1 + src/northbridge/via/vx900/romstrap.S | 56 +++++++++ src/northbridge/via/vx900/romstrap.inc | 56 --------- src/southbridge/nvidia/ck804/Kconfig | 4 - src/southbridge/nvidia/ck804/Makefile.inc | 1 + src/southbridge/nvidia/ck804/romstrap.S | 55 +++++++++ src/southbridge/nvidia/ck804/romstrap.inc | 55 --------- src/southbridge/nvidia/mcp55/Kconfig | 4 - src/southbridge/nvidia/mcp55/Makefile.inc | 1 + src/southbridge/nvidia/mcp55/romstrap.S | 55 +++++++++ src/southbridge/nvidia/mcp55/romstrap.inc | 55 --------- src/southbridge/sis/sis966/Kconfig | 4 - src/southbridge/sis/sis966/Makefile.inc | 1 + src/southbridge/sis/sis966/romstrap.S | 62 ++++++++++ src/southbridge/sis/sis966/romstrap.inc | 62 ---------- src/southbridge/via/k8t890/Kconfig | 4 - src/southbridge/via/k8t890/Makefile.inc | 1 + src/southbridge/via/k8t890/romstrap.S | 99 +++++++++++++++ src/southbridge/via/k8t890/romstrap.inc | 99 --------------- 31 files changed, 634 insertions(+), 660 deletions(-)
diff --git a/src/cpu/dmp/vortex86ex/Kconfig b/src/cpu/dmp/vortex86ex/Kconfig index 1f43f76..1af7ec4 100644 --- a/src/cpu/dmp/vortex86ex/Kconfig +++ b/src/cpu/dmp/vortex86ex/Kconfig @@ -73,8 +73,4 @@ config PLL_500_375_33
endchoice
-config CHIPSET_BOOTBLOCK_INCLUDE - string - default "cpu/dmp/vortex86ex/chipset_bootblock.inc" - endif diff --git a/src/cpu/dmp/vortex86ex/Makefile.inc b/src/cpu/dmp/vortex86ex/Makefile.inc index 76df34c..6b4d0ba 100644 --- a/src/cpu/dmp/vortex86ex/Makefile.inc +++ b/src/cpu/dmp/vortex86ex/Makefile.inc @@ -21,5 +21,7 @@ subdirs-y += ../../x86/smm
bootblock-y += biosdata.ld bootblock-y += biosdata_ex.ld +bootblock-y += biosdata.S +bootblock-y += biosdata_ex.S
ROMCCFLAGS := -mcpu=i386 -O2 diff --git a/src/cpu/dmp/vortex86ex/biosdata.S b/src/cpu/dmp/vortex86ex/biosdata.S new file mode 100644 index 0000000..c08242a --- /dev/null +++ b/src/cpu/dmp/vortex86ex/biosdata.S @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + .section ".dmp_reserved", "a", @progbits + + .skip 0x3c000 - 0x3bc00, 0xff + +.previous + + .section ".dmp_kbd_fw_part2", "a", @progbits + + .skip 0x3d000 - 0x3c000, 0xff + +.previous + + .section ".dmp_mtbf_low_cnt", "a", @progbits + + .skip 0x3e000 - 0x3d000, 0xff + +.previous + + .section ".dmp_kbd_fw_part1", "a", @progbits + + #include "dmp_kbd_fw_part1.inc" + +.previous + + .section ".dmp_spi_flash_disk_driver", "a", @progbits + + .skip 0x3f800 - 0x3f000, 0xff + +.previous + + .section ".dmp_frontdoor", "a", @progbits + + .skip 0x3fd00 - 0x3f800, 0xff + +.previous + + .section ".dmp_isoinfo", "a", @progbits + + .skip 26 * 16, 0xff + +.previous + + .section ".dmp_isodata_checksum", "a", @progbits + + .skip 8, 0xff + +.previous + + .section ".dmp_mac", "a", @progbits + + .skip 6, 0xff + +.previous + + .section ".dmp_mtbf_limit", "a", @progbits + + .skip 3, 0xff + +.previous + + .section ".dmp_isodata", "a", @progbits + + .skip 32, 0xff + +.previous diff --git a/src/cpu/dmp/vortex86ex/biosdata.inc b/src/cpu/dmp/vortex86ex/biosdata.inc deleted file mode 100644 index c08242a..0000000 --- a/src/cpu/dmp/vortex86ex/biosdata.inc +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 DMP Electronics Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - .section ".dmp_reserved", "a", @progbits - - .skip 0x3c000 - 0x3bc00, 0xff - -.previous - - .section ".dmp_kbd_fw_part2", "a", @progbits - - .skip 0x3d000 - 0x3c000, 0xff - -.previous - - .section ".dmp_mtbf_low_cnt", "a", @progbits - - .skip 0x3e000 - 0x3d000, 0xff - -.previous - - .section ".dmp_kbd_fw_part1", "a", @progbits - - #include "dmp_kbd_fw_part1.inc" - -.previous - - .section ".dmp_spi_flash_disk_driver", "a", @progbits - - .skip 0x3f800 - 0x3f000, 0xff - -.previous - - .section ".dmp_frontdoor", "a", @progbits - - .skip 0x3fd00 - 0x3f800, 0xff - -.previous - - .section ".dmp_isoinfo", "a", @progbits - - .skip 26 * 16, 0xff - -.previous - - .section ".dmp_isodata_checksum", "a", @progbits - - .skip 8, 0xff - -.previous - - .section ".dmp_mac", "a", @progbits - - .skip 6, 0xff - -.previous - - .section ".dmp_mtbf_limit", "a", @progbits - - .skip 3, 0xff - -.previous - - .section ".dmp_isodata", "a", @progbits - - .skip 32, 0xff - -.previous diff --git a/src/cpu/dmp/vortex86ex/biosdata_ex.S b/src/cpu/dmp/vortex86ex/biosdata_ex.S new file mode 100644 index 0000000..5ed17c6 --- /dev/null +++ b/src/cpu/dmp/vortex86ex/biosdata_ex.S @@ -0,0 +1,172 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "config.h" + +/* +PLL Freq = 25 * NS /(MS * 2^RS) +CPU Freq = PLL/(CPU_DIV+2) +DRAM Freq = PLL/2(DRAM_DIV+1) + +DDR3 +CPU/DRAM/PCI B6 B7 BB BC BD BF +200/200/33 30 03 0F 02 8F 07 +300/300/33 48 03 0F 02 1F 07 +300/300/33 48 03 0F 3A DF 07 ; write leveling disable, cpu bypass disable +300/300/33 48 03 0F 22 3F 07 ; cpu bypass disable +300/300/100 48 03 23 02 7F 07 +400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing +400/200/100 60 43 23 02 4F 07 +400/400/33 60 03 0F 02 BF 09 +500/250/33 50 42 0F 02 DF 07 +500/500/33 78 03 0F 02 4F 09 +400/300/33 90 53 0F 02 3F 07 +400/300/33 90 53 0F 1A DF 07 ; write leveling/gate training disable +400/300/100 90 53 23 02 9F 07 +444/333/33 A0 53 0F 02 5F 08 +466/350/33 A8 53 0F 02 DF 09 +500/375/33 B4 53 0F 02 AF 09 +*/ + +#if CONFIG_PLL_200_200_33 + // 200/200/33 30 03 0F 02 8F 07 + byte_fffb6 = 0x30 + byte_fffb7 = 0x03 + byte_fffbb = 0x0f + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x07 +#elif CONFIG_PLL_300_300_33 + // 300/300/33 48 03 0F 02 1F 07 + byte_fffb6 = 0x48 + byte_fffb7 = 0x03 + byte_fffbb = 0x0f + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x07 +#elif CONFIG_PLL_300_300_100 + // 300/300/100 48 03 23 02 7F 07 + byte_fffb6 = 0x48 + byte_fffb7 = 0x03 + byte_fffbb = 0x23 + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x07 +#elif CONFIG_PLL_400_200_33 + // 400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing + byte_fffb6 = 0x60 + byte_fffb7 = 0x43 + byte_fffbb = 0x0f + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x07 +#elif CONFIG_PLL_400_200_100 + // 400/200/100 60 43 23 02 4F 07 + byte_fffb6 = 0x60 + byte_fffb7 = 0x43 + byte_fffbb = 0x23 + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x07 +#elif CONFIG_PLL_400_400_33 + // 400/400/33 60 03 0F 02 BF 09 + byte_fffb6 = 0x60 + byte_fffb7 = 0x03 + byte_fffbb = 0x0f + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x09 +#elif CONFIG_PLL_500_250_33 + // 500/250/33 50 42 0F 02 DF 07 + byte_fffb6 = 0x50 + byte_fffb7 = 0x42 + byte_fffbb = 0x0f + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x07 +#elif CONFIG_PLL_500_500_33 + // 500/500/33 78 03 0F 02 4F 09 + byte_fffb6 = 0x78 + byte_fffb7 = 0x03 + byte_fffbb = 0x0f + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x09 +#elif CONFIG_PLL_400_300_33 + // 400/300/33 90 53 0F 02 3F 07 + byte_fffb6 = 0x90 + byte_fffb7 = 0x53 + byte_fffbb = 0x0f + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x07 +#elif CONFIG_PLL_400_300_100 + // 400/300/100 90 53 23 02 9F 07 + byte_fffb6 = 0x90 + byte_fffb7 = 0x53 + byte_fffbb = 0x23 + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x07 +#elif CONFIG_PLL_444_333_33 + // 444/333/33 A0 53 0F 02 5F 08 + byte_fffb6 = 0xa0 + byte_fffb7 = 0x53 + byte_fffbb = 0x0f + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x08 +#elif CONFIG_PLL_466_350_33 + // 466/350/33 A8 53 0F 02 DF 09 + byte_fffb6 = 0xa8 + byte_fffb7 = 0x53 + byte_fffbb = 0x0f + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x09 +#elif CONFIG_PLL_500_375_33 + // 500/375/33 B4 53 0F 02 AF 09 + byte_fffb6 = 0xb4 + byte_fffb7 = 0x53 + byte_fffbb = 0x0f + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x09 +#else + #error Error Strap PLL config. +#endif + +tmp_sum = byte_fffb6 + byte_fffb7 + byte_fffbb + byte_fffbc +pll_checksum = ((tmp_sum >> 8) & 0x3) + ((tmp_sum >> 4) & 0x0f) + (tmp_sum & 0x0f) + +byte_fffbd = ((pll_checksum & 0x0f) << 4) | 0x0f + + .section ".a9123_crossbar_config", "a", @progbits + + .skip 0x3fdf0 - 0x3fd00, 0xff + +.previous + + .section ".a9123_strap_1", "a", @progbits + + .byte byte_fffb6, byte_fffb7 + +.previous + + .section ".a9123_strap_2", "a", @progbits + + .byte byte_fffbb, byte_fffbc, byte_fffbd, byte_fffbe, byte_fffbf + +.previous diff --git a/src/cpu/dmp/vortex86ex/biosdata_ex.inc b/src/cpu/dmp/vortex86ex/biosdata_ex.inc deleted file mode 100644 index 5ed17c6..0000000 --- a/src/cpu/dmp/vortex86ex/biosdata_ex.inc +++ /dev/null @@ -1,172 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 DMP Electronics Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "config.h" - -/* -PLL Freq = 25 * NS /(MS * 2^RS) -CPU Freq = PLL/(CPU_DIV+2) -DRAM Freq = PLL/2(DRAM_DIV+1) - -DDR3 -CPU/DRAM/PCI B6 B7 BB BC BD BF -200/200/33 30 03 0F 02 8F 07 -300/300/33 48 03 0F 02 1F 07 -300/300/33 48 03 0F 3A DF 07 ; write leveling disable, cpu bypass disable -300/300/33 48 03 0F 22 3F 07 ; cpu bypass disable -300/300/100 48 03 23 02 7F 07 -400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing -400/200/100 60 43 23 02 4F 07 -400/400/33 60 03 0F 02 BF 09 -500/250/33 50 42 0F 02 DF 07 -500/500/33 78 03 0F 02 4F 09 -400/300/33 90 53 0F 02 3F 07 -400/300/33 90 53 0F 1A DF 07 ; write leveling/gate training disable -400/300/100 90 53 23 02 9F 07 -444/333/33 A0 53 0F 02 5F 08 -466/350/33 A8 53 0F 02 DF 09 -500/375/33 B4 53 0F 02 AF 09 -*/ - -#if CONFIG_PLL_200_200_33 - // 200/200/33 30 03 0F 02 8F 07 - byte_fffb6 = 0x30 - byte_fffb7 = 0x03 - byte_fffbb = 0x0f - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x07 -#elif CONFIG_PLL_300_300_33 - // 300/300/33 48 03 0F 02 1F 07 - byte_fffb6 = 0x48 - byte_fffb7 = 0x03 - byte_fffbb = 0x0f - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x07 -#elif CONFIG_PLL_300_300_100 - // 300/300/100 48 03 23 02 7F 07 - byte_fffb6 = 0x48 - byte_fffb7 = 0x03 - byte_fffbb = 0x23 - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x07 -#elif CONFIG_PLL_400_200_33 - // 400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing - byte_fffb6 = 0x60 - byte_fffb7 = 0x43 - byte_fffbb = 0x0f - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x07 -#elif CONFIG_PLL_400_200_100 - // 400/200/100 60 43 23 02 4F 07 - byte_fffb6 = 0x60 - byte_fffb7 = 0x43 - byte_fffbb = 0x23 - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x07 -#elif CONFIG_PLL_400_400_33 - // 400/400/33 60 03 0F 02 BF 09 - byte_fffb6 = 0x60 - byte_fffb7 = 0x03 - byte_fffbb = 0x0f - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x09 -#elif CONFIG_PLL_500_250_33 - // 500/250/33 50 42 0F 02 DF 07 - byte_fffb6 = 0x50 - byte_fffb7 = 0x42 - byte_fffbb = 0x0f - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x07 -#elif CONFIG_PLL_500_500_33 - // 500/500/33 78 03 0F 02 4F 09 - byte_fffb6 = 0x78 - byte_fffb7 = 0x03 - byte_fffbb = 0x0f - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x09 -#elif CONFIG_PLL_400_300_33 - // 400/300/33 90 53 0F 02 3F 07 - byte_fffb6 = 0x90 - byte_fffb7 = 0x53 - byte_fffbb = 0x0f - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x07 -#elif CONFIG_PLL_400_300_100 - // 400/300/100 90 53 23 02 9F 07 - byte_fffb6 = 0x90 - byte_fffb7 = 0x53 - byte_fffbb = 0x23 - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x07 -#elif CONFIG_PLL_444_333_33 - // 444/333/33 A0 53 0F 02 5F 08 - byte_fffb6 = 0xa0 - byte_fffb7 = 0x53 - byte_fffbb = 0x0f - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x08 -#elif CONFIG_PLL_466_350_33 - // 466/350/33 A8 53 0F 02 DF 09 - byte_fffb6 = 0xa8 - byte_fffb7 = 0x53 - byte_fffbb = 0x0f - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x09 -#elif CONFIG_PLL_500_375_33 - // 500/375/33 B4 53 0F 02 AF 09 - byte_fffb6 = 0xb4 - byte_fffb7 = 0x53 - byte_fffbb = 0x0f - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x09 -#else - #error Error Strap PLL config. -#endif - -tmp_sum = byte_fffb6 + byte_fffb7 + byte_fffbb + byte_fffbc -pll_checksum = ((tmp_sum >> 8) & 0x3) + ((tmp_sum >> 4) & 0x0f) + (tmp_sum & 0x0f) - -byte_fffbd = ((pll_checksum & 0x0f) << 4) | 0x0f - - .section ".a9123_crossbar_config", "a", @progbits - - .skip 0x3fdf0 - 0x3fd00, 0xff - -.previous - - .section ".a9123_strap_1", "a", @progbits - - .byte byte_fffb6, byte_fffb7 - -.previous - - .section ".a9123_strap_2", "a", @progbits - - .byte byte_fffbb, byte_fffbc, byte_fffbd, byte_fffbe, byte_fffbf - -.previous diff --git a/src/cpu/dmp/vortex86ex/chipset_bootblock.inc b/src/cpu/dmp/vortex86ex/chipset_bootblock.inc deleted file mode 100644 index bdcda1d..0000000 --- a/src/cpu/dmp/vortex86ex/chipset_bootblock.inc +++ /dev/null @@ -1,2 +0,0 @@ -#include "biosdata.inc" -#include "biosdata_ex.inc" diff --git a/src/northbridge/via/vx800/Kconfig b/src/northbridge/via/vx800/Kconfig index d7d5349..9eb84fb 100644 --- a/src/northbridge/via/vx800/Kconfig +++ b/src/northbridge/via/vx800/Kconfig @@ -3,11 +3,3 @@ config NORTHBRIDGE_VIA_VX800 select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_SMBUS select LATE_CBMEM_INIT - -if NORTHBRIDGE_VIA_VX800 - -config CHIPSET_BOOTBLOCK_INCLUDE - string - default "northbridge/via/vx800/romstrap.inc" - -endif diff --git a/src/northbridge/via/vx800/Makefile.inc b/src/northbridge/via/vx800/Makefile.inc index 069ea8e..90574ed 100644 --- a/src/northbridge/via/vx800/Makefile.inc +++ b/src/northbridge/via/vx800/Makefile.inc @@ -22,5 +22,6 @@ ramstage-y += lpc.c ramstage-y += ide.c
bootblock-y += romstrap.ld +bootblock-y += romstrap.S
endif diff --git a/src/northbridge/via/vx800/romstrap.S b/src/northbridge/via/vx800/romstrap.S new file mode 100644 index 0000000..82b5b4b --- /dev/null +++ b/src/northbridge/via/vx800/romstrap.S @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * (Written by Yinghai Lu yhlu@tyan.com for Tyan Computer) + * Copyright (C) 2007 Rudolf Marek r.marek@assembler.cz + * Copyright (C) 2009 One Laptop per Child, Association, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This file constructs the ROM strap table for K8T890 and K8M890 */ + + .section ".romstrap", "a", @progbits + + .globl __romstrap_start +__romstrap_start: +tblpointer: + .long 0x55aa66cc + .long 0x88012554 + .long 0x77107777 + .long 0x00770814 + + + .long 0x00000000 + .long 0x00000000 + .long 0x00000000 + .long 0x00000000 + +/* + * The pointer to above table should be at 0xffffffd0, + * the table itself MUST be aligned to 128B it seems! + */ +rspointers: + .long tblpointer // It will be 0xffffffd0 + + .globl __romstrap_end + +__romstrap_end: +.previous diff --git a/src/northbridge/via/vx800/romstrap.inc b/src/northbridge/via/vx800/romstrap.inc deleted file mode 100644 index 82b5b4b..0000000 --- a/src/northbridge/via/vx800/romstrap.inc +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * (Written by Yinghai Lu yhlu@tyan.com for Tyan Computer) - * Copyright (C) 2007 Rudolf Marek r.marek@assembler.cz - * Copyright (C) 2009 One Laptop per Child, Association, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file constructs the ROM strap table for K8T890 and K8M890 */ - - .section ".romstrap", "a", @progbits - - .globl __romstrap_start -__romstrap_start: -tblpointer: - .long 0x55aa66cc - .long 0x88012554 - .long 0x77107777 - .long 0x00770814 - - - .long 0x00000000 - .long 0x00000000 - .long 0x00000000 - .long 0x00000000 - -/* - * The pointer to above table should be at 0xffffffd0, - * the table itself MUST be aligned to 128B it seems! - */ -rspointers: - .long tblpointer // It will be 0xffffffd0 - - .globl __romstrap_end - -__romstrap_end: -.previous diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig index c7641d1..2d2dffa 100644 --- a/src/northbridge/via/vx900/Kconfig +++ b/src/northbridge/via/vx900/Kconfig @@ -39,8 +39,4 @@ config VGA_BIOS_ID string default "1106,7122"
-config CHIPSET_BOOTBLOCK_INCLUDE - string - default "northbridge/via/vx900/romstrap.inc" - endif diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc index 4cac1e7..44f0ae0 100644 --- a/src/northbridge/via/vx900/Makefile.inc +++ b/src/northbridge/via/vx900/Makefile.inc @@ -44,5 +44,6 @@ ramstage-y += ./../../../drivers/pc80/vga/vga_io.c
bootblock-y += romstrap.ld +bootblock-y += romstrap.S
endif diff --git a/src/northbridge/via/vx900/romstrap.S b/src/northbridge/via/vx900/romstrap.S new file mode 100644 index 0000000..26c1ee6 --- /dev/null +++ b/src/northbridge/via/vx900/romstrap.S @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * (Written by Yinghai Lu yhlu@tyan.com for Tyan Computer) + * Copyright (C) 2007 Rudolf Marek r.marek@assembler.cz + * Copyright (C) 2009 One Laptop per Child, Association, Inc. + * Copyright (C) 2011-2012 Alexandru Gagniuc mr.nuke.me@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* As extracted from the manufacturer's ROM, the romstrap table looks like: + * .long 0x77886047 .long 0x00777777 + * .long 0x00000000 .long 0x00000000 + * .long 0x00888888 .long 0x00AA1111 + * .long 0x00000000 .long 0x00000000 + * + * The vendor BIOS then adjusts some of these settings very early on. Instead of + * adjusting those settings in code, we work them in the romstrap table. + * + */ +/* This file constructs the ROM strap table for VX900 */ + + .section ".romstrap", "a", @progbits + + .globl __romstrap_start +__romstrap_start: +tblpointer: + .long 0x77886047 + .long 0x00777777 + .long 0x00000000 + .long 0x00000000 + .long 0x00888888 + .long 0x00AA1111 + .long 0x00000000 + .long 0x00000000 + +/* + * The pointer to above table should be at 0xffffffd0, + * the table itself MUST be aligned to 128B it seems! + */ +rspointers: + .long tblpointer // It will be 0xffffffd0 + + .globl __romstrap_end + +__romstrap_end: +.previous diff --git a/src/northbridge/via/vx900/romstrap.inc b/src/northbridge/via/vx900/romstrap.inc deleted file mode 100644 index 26c1ee6..0000000 --- a/src/northbridge/via/vx900/romstrap.inc +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * (Written by Yinghai Lu yhlu@tyan.com for Tyan Computer) - * Copyright (C) 2007 Rudolf Marek r.marek@assembler.cz - * Copyright (C) 2009 One Laptop per Child, Association, Inc. - * Copyright (C) 2011-2012 Alexandru Gagniuc mr.nuke.me@gmail.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* As extracted from the manufacturer's ROM, the romstrap table looks like: - * .long 0x77886047 .long 0x00777777 - * .long 0x00000000 .long 0x00000000 - * .long 0x00888888 .long 0x00AA1111 - * .long 0x00000000 .long 0x00000000 - * - * The vendor BIOS then adjusts some of these settings very early on. Instead of - * adjusting those settings in code, we work them in the romstrap table. - * - */ -/* This file constructs the ROM strap table for VX900 */ - - .section ".romstrap", "a", @progbits - - .globl __romstrap_start -__romstrap_start: -tblpointer: - .long 0x77886047 - .long 0x00777777 - .long 0x00000000 - .long 0x00000000 - .long 0x00888888 - .long 0x00AA1111 - .long 0x00000000 - .long 0x00000000 - -/* - * The pointer to above table should be at 0xffffffd0, - * the table itself MUST be aligned to 128B it seems! - */ -rspointers: - .long tblpointer // It will be 0xffffffd0 - - .globl __romstrap_end - -__romstrap_end: -.previous diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig index 42dce07..dbd24b7 100644 --- a/src/southbridge/nvidia/ck804/Kconfig +++ b/src/southbridge/nvidia/ck804/Kconfig @@ -42,8 +42,4 @@ config HPET_MIN_TICKS hex default 0xfa
-config CHIPSET_BOOTBLOCK_INCLUDE - string - default "southbridge/nvidia/ck804/romstrap.inc" - endif diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc index 69dd4b2..554a440 100644 --- a/src/southbridge/nvidia/ck804/Makefile.inc +++ b/src/southbridge/nvidia/ck804/Makefile.inc @@ -22,5 +22,6 @@ ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_smbus.c
bootblock-y += romstrap.ld +bootblock-y += romstrap.S
endif diff --git a/src/southbridge/nvidia/ck804/romstrap.S b/src/southbridge/nvidia/ck804/romstrap.S new file mode 100644 index 0000000..5a20107 --- /dev/null +++ b/src/southbridge/nvidia/ck804/romstrap.S @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu yhlu@tyan.com for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + .section ".romstrap", "a", @progbits + + + .align 16 + .globl __romstrap_start +__romstrap_start: +rstables: + .long 0x2b16d065 + .long 0x0 + .long 0x0 + .long linkedlist + +linkedlist: + .long 0x0003001C // 10h + .long 0x08000000 // 14h + .long 0x00000000 // 18h + .long 0xFFFFFFFF // 1Ch + + .long 0xFFFFFFFF // 20h + .long 0xFFFFFFFF // 24h + .long 0xFFFFFFFF // 28h + .long 0xFFFFFFFF // 2Ch + + .long 0x81543266 // 30h, MAC address low 4 byte ---> keep it in 0xffffffd0 + .long 0x000000E0 // 34h, MAC address high 4 byte + + .long 0x002309CE // 38h, UUID low 4 byte + .long 0x00E08100 // 3Ch, UUID high 4 byte + +rspointers: + .long rstables // It will be 0xffffffe0 + .long rstables + .long rstables + .long rstables + + .globl __romstrap_end + +__romstrap_end: +.previous diff --git a/src/southbridge/nvidia/ck804/romstrap.inc b/src/southbridge/nvidia/ck804/romstrap.inc deleted file mode 100644 index 5a20107..0000000 --- a/src/southbridge/nvidia/ck804/romstrap.inc +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu yhlu@tyan.com for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - .section ".romstrap", "a", @progbits - - - .align 16 - .globl __romstrap_start -__romstrap_start: -rstables: - .long 0x2b16d065 - .long 0x0 - .long 0x0 - .long linkedlist - -linkedlist: - .long 0x0003001C // 10h - .long 0x08000000 // 14h - .long 0x00000000 // 18h - .long 0xFFFFFFFF // 1Ch - - .long 0xFFFFFFFF // 20h - .long 0xFFFFFFFF // 24h - .long 0xFFFFFFFF // 28h - .long 0xFFFFFFFF // 2Ch - - .long 0x81543266 // 30h, MAC address low 4 byte ---> keep it in 0xffffffd0 - .long 0x000000E0 // 34h, MAC address high 4 byte - - .long 0x002309CE // 38h, UUID low 4 byte - .long 0x00E08100 // 3Ch, UUID high 4 byte - -rspointers: - .long rstables // It will be 0xffffffe0 - .long rstables - .long rstables - .long rstables - - .globl __romstrap_end - -__romstrap_end: -.previous diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig index 666d3f8..89aa452 100644 --- a/src/southbridge/nvidia/mcp55/Kconfig +++ b/src/southbridge/nvidia/mcp55/Kconfig @@ -42,8 +42,4 @@ config MCP55_PCI_E_X_3 int default 4
-config CHIPSET_BOOTBLOCK_INCLUDE - string - default "southbridge/nvidia/mcp55/romstrap.inc" - endif diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc index 74ef14c..db275cc 100644 --- a/src/southbridge/nvidia/mcp55/Makefile.inc +++ b/src/southbridge/nvidia/mcp55/Makefile.inc @@ -25,5 +25,6 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c endif
bootblock-y += romstrap.ld +bootblock-y += romstrap.S
endif diff --git a/src/southbridge/nvidia/mcp55/romstrap.S b/src/southbridge/nvidia/mcp55/romstrap.S new file mode 100644 index 0000000..ff170a9 --- /dev/null +++ b/src/southbridge/nvidia/mcp55/romstrap.S @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu yhlu@tyan.com for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + .section ".romstrap", "a", @progbits + + + .globl __romstrap_start +__romstrap_start: +rstables: + .long 0x2b16d065 + .long 0x0 + .long 0x0 + .long linkedlist + +linkedlist: + .long 0x0003001C // 10h + .long 0x08000000 // 14h + .long 0x00000000 // 18h + .long 0xFFFFFFFF // 1Ch + + .long 0xFFFFFFFF // 20h + .long 0xFFFFFFFF // 24h + .long 0xFFFFFFFF // 28h + .long 0xFFFFFFFF // 2Ch + + .long 0x81543266 // 30h, MAC address low 4 byte ---> keep it in 0xffffffd0 + .long 0x000000E0 // 34h, MAC address high 4 byte + + .long 0x002309CE // 38h, UUID low 4 byte + .long 0x00E08100 // 3Ch, UUID high 4 byte + +rspointers: + .long rstables // It will be 0xffffffe0 + .long rstables + .long rstables + .long rstables + + .globl __romstrap_end + +__romstrap_end: +.previous diff --git a/src/southbridge/nvidia/mcp55/romstrap.inc b/src/southbridge/nvidia/mcp55/romstrap.inc deleted file mode 100644 index ff170a9..0000000 --- a/src/southbridge/nvidia/mcp55/romstrap.inc +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu yhlu@tyan.com for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - .section ".romstrap", "a", @progbits - - - .globl __romstrap_start -__romstrap_start: -rstables: - .long 0x2b16d065 - .long 0x0 - .long 0x0 - .long linkedlist - -linkedlist: - .long 0x0003001C // 10h - .long 0x08000000 // 14h - .long 0x00000000 // 18h - .long 0xFFFFFFFF // 1Ch - - .long 0xFFFFFFFF // 20h - .long 0xFFFFFFFF // 24h - .long 0xFFFFFFFF // 28h - .long 0xFFFFFFFF // 2Ch - - .long 0x81543266 // 30h, MAC address low 4 byte ---> keep it in 0xffffffd0 - .long 0x000000E0 // 34h, MAC address high 4 byte - - .long 0x002309CE // 38h, UUID low 4 byte - .long 0x00E08100 // 3Ch, UUID high 4 byte - -rspointers: - .long rstables // It will be 0xffffffe0 - .long rstables - .long rstables - .long rstables - - .globl __romstrap_end - -__romstrap_end: -.previous diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig index 20f3bff..c6023a9 100644 --- a/src/southbridge/sis/sis966/Kconfig +++ b/src/southbridge/sis/sis966/Kconfig @@ -14,8 +14,4 @@ config EHCI_BAR hex default 0xfef00000
-config CHIPSET_BOOTBLOCK_INCLUDE - string - default "southbridge/sis/sis966/romstrap.inc" - endif diff --git a/src/southbridge/sis/sis966/Makefile.inc b/src/southbridge/sis/sis966/Makefile.inc index e703e1f..fa37762 100644 --- a/src/southbridge/sis/sis966/Makefile.inc +++ b/src/southbridge/sis/sis966/Makefile.inc @@ -16,5 +16,6 @@ romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
bootblock-y += romstrap.ld +bootblock-y += romstrap.S
endif diff --git a/src/southbridge/sis/sis966/romstrap.S b/src/southbridge/sis/sis966/romstrap.S new file mode 100644 index 0000000..1eb39e3 --- /dev/null +++ b/src/southbridge/sis/sis966/romstrap.S @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu yhlu@tyan.com for Tyan Computer. + * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) + * Written by Morgan Tsai my_tsai@sis.com for SiS. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + .section ".romstrap", "a", @progbits + + + .globl __romstrap_start +__romstrap_start: +rstables: + .long 0x2b16d065 + .long 0x0 + .long 0x0 + .long linkedlist + +linkedlist: + .long 0x0003001C // 10h + .long 0x08000000 // 14h + .long 0x00000000 // 18h + .long 0xFFFFFFFF // 1Ch + + .long 0xFFFFFFFF // 20h + .long 0xFFFFFFFF // 24h + .long 0xFFFFFFFF // 28h + .long 0xFFFFFFFF // 2Ch + + .long 0x56341200 // 30h, MAC address low 4 byte ---> keep it in 0xffffffc0 + .long 0x00009078 // 34h, MAC address high 4 byte + + .long 0x002309CE // 38h, UUID low 4 byte + .long 0x00E08100 // 3Ch, UUID high 4 byte + + .long 0x00402000 //Firmware trap for SiS761+966 + .long 0xE043A800 + .long 0x00180000 + .long 0x1421C402 + +rspointers: + .long rstables // It will be 0xffffffe0 + .long rstables + .long rstables + .long rstables + + .globl __romstrap_end + +__romstrap_end: +.previous diff --git a/src/southbridge/sis/sis966/romstrap.inc b/src/southbridge/sis/sis966/romstrap.inc deleted file mode 100644 index 1eb39e3..0000000 --- a/src/southbridge/sis/sis966/romstrap.inc +++ /dev/null @@ -1,62 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu yhlu@tyan.com for Tyan Computer. - * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) - * Written by Morgan Tsai my_tsai@sis.com for SiS. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - .section ".romstrap", "a", @progbits - - - .globl __romstrap_start -__romstrap_start: -rstables: - .long 0x2b16d065 - .long 0x0 - .long 0x0 - .long linkedlist - -linkedlist: - .long 0x0003001C // 10h - .long 0x08000000 // 14h - .long 0x00000000 // 18h - .long 0xFFFFFFFF // 1Ch - - .long 0xFFFFFFFF // 20h - .long 0xFFFFFFFF // 24h - .long 0xFFFFFFFF // 28h - .long 0xFFFFFFFF // 2Ch - - .long 0x56341200 // 30h, MAC address low 4 byte ---> keep it in 0xffffffc0 - .long 0x00009078 // 34h, MAC address high 4 byte - - .long 0x002309CE // 38h, UUID low 4 byte - .long 0x00E08100 // 3Ch, UUID high 4 byte - - .long 0x00402000 //Firmware trap for SiS761+966 - .long 0xE043A800 - .long 0x00180000 - .long 0x1421C402 - -rspointers: - .long rstables // It will be 0xffffffe0 - .long rstables - .long rstables - .long rstables - - .globl __romstrap_end - -__romstrap_end: -.previous diff --git a/src/southbridge/via/k8t890/Kconfig b/src/southbridge/via/k8t890/Kconfig index 76be0c1..f6e51dc 100644 --- a/src/southbridge/via/k8t890/Kconfig +++ b/src/southbridge/via/k8t890/Kconfig @@ -51,8 +51,4 @@ config VIDEO_MB default -1 if K8M890_VIDEO_MB_CMOS depends on SOUTHBRIDGE_VIA_K8M890_VGA_EN
-config CHIPSET_BOOTBLOCK_INCLUDE - string - default "southbridge/via/k8t890/romstrap.inc" - endif # SOUTHBRIDGE_K8T890 diff --git a/src/southbridge/via/k8t890/Makefile.inc b/src/southbridge/via/k8t890/Makefile.inc index 2789499..ed6d3ed 100644 --- a/src/southbridge/via/k8t890/Makefile.inc +++ b/src/southbridge/via/k8t890/Makefile.inc @@ -11,5 +11,6 @@ ramstage-y += error.c ramstage-y += chrome.c
bootblock-y += romstrap.ld +bootblock-y += romstrap.S
endif diff --git a/src/southbridge/via/k8t890/romstrap.S b/src/southbridge/via/k8t890/romstrap.S new file mode 100644 index 0000000..2115eaa --- /dev/null +++ b/src/southbridge/via/k8t890/romstrap.S @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * (Written by Yinghai Lu yhlu@tyan.com for Tyan Computer) + * Copyright (C) 2007 Rudolf Marek r.marek@assembler.cz + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This file constructs the ROM strap table for K8T890 and K8M890 */ + +.section ".romstrap", "a", @progbits + +.globl __romstrap_start +.globl __romstrap_end + +__romstrap_start: + +/* + * Below are some Dev0 Func2 HT control registers values, + * depending on strap pin, one of below lines is used. + */ +#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M800 || CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800 || CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD + +tblpointer: +.long 0x50220000, 0X619707C2 +.long 0x50220000, 0X619707C2 +.long 0x50220000, 0X619707C2 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 + +#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890 + +tblpointer: +.long 0x504400FF, 0x61970FC2 //;200M +.long 0x504400FF, 0x61970FC2 //;400M +.long 0x504400FF, 0x61970FC2 //;600M +.long 0x504400FF, 0x61970FC2 //;800M +.long 0x504400FF, 0x61970FC2 //;1000M +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 + + +#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T890 + +tblpointer: +.long 0x504400AA, 0x61970FC2 //;200M +.long 0x504400AA, 0x61970FC2 //;400M +.long 0x504400AA, 0x61970FC2 //;600M +.long 0x504400AA, 0x61970FC2 //;800M +.long 0x504400AA, 0x61970FC2 //;1000M +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 + +#endif +/* + * The pointer to above table should be at 0xffffd, + * the table itself MUST be aligned to 128B it seems! + */ +.long tblpointer - 0xFFF00000 + +__romstrap_end: + +.previous diff --git a/src/southbridge/via/k8t890/romstrap.inc b/src/southbridge/via/k8t890/romstrap.inc deleted file mode 100644 index 2115eaa..0000000 --- a/src/southbridge/via/k8t890/romstrap.inc +++ /dev/null @@ -1,99 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * (Written by Yinghai Lu yhlu@tyan.com for Tyan Computer) - * Copyright (C) 2007 Rudolf Marek r.marek@assembler.cz - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file constructs the ROM strap table for K8T890 and K8M890 */ - -.section ".romstrap", "a", @progbits - -.globl __romstrap_start -.globl __romstrap_end - -__romstrap_start: - -/* - * Below are some Dev0 Func2 HT control registers values, - * depending on strap pin, one of below lines is used. - */ -#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M800 || CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800 || CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD - -tblpointer: -.long 0x50220000, 0X619707C2 -.long 0x50220000, 0X619707C2 -.long 0x50220000, 0X619707C2 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 - -#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890 - -tblpointer: -.long 0x504400FF, 0x61970FC2 //;200M -.long 0x504400FF, 0x61970FC2 //;400M -.long 0x504400FF, 0x61970FC2 //;600M -.long 0x504400FF, 0x61970FC2 //;800M -.long 0x504400FF, 0x61970FC2 //;1000M -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 - - -#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T890 - -tblpointer: -.long 0x504400AA, 0x61970FC2 //;200M -.long 0x504400AA, 0x61970FC2 //;400M -.long 0x504400AA, 0x61970FC2 //;600M -.long 0x504400AA, 0x61970FC2 //;800M -.long 0x504400AA, 0x61970FC2 //;1000M -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 -.long 0x0 - -#endif -/* - * The pointer to above table should be at 0xffffd, - * the table itself MUST be aligned to 128B it seems! - */ -.long tblpointer - 0xFFF00000 - -__romstrap_end: - -.previous
-
Alexandru Gagniuc