Change in coreboot[master]: soc/inteL/broadwell: Move select CHROMEOS_RAMOOPS_DYNAMIC

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50604 )

Change subject: soc/inteL/broadwell: Move select CHROMEOS_RAMOOPS_DYNAMIC
......................................................................

soc/inteL/broadwell: Move select CHROMEOS_RAMOOPS_DYNAMIC

With this selected, chromeos_reserve_ram_oops() is a no-op.

Change-Id: I2f3b7b3c4a9549a14f2ba039c769546f9698409a
Signed-off-by: Kyösti Mälkki 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50604
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
---
M src/mainboard/google/auron/Kconfig
M src/mainboard/google/jecht/Kconfig
M src/mainboard/intel/wtm2/Kconfig
M src/soc/intel/broadwell/Kconfig
M src/soc/intel/broadwell/northbridge.c
5 files changed, 3 insertions(+), 13 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig
index 5301e32..45e4e3af 100644
--- a/src/mainboard/google/auron/Kconfig
+++ b/src/mainboard/google/auron/Kconfig
@@ -19,9 +19,6 @@

if BOARD_GOOGLE_BASEBOARD_AURON

-config CHROMEOS
-	select CHROMEOS_RAMOOPS_DYNAMIC
-
 config VBOOT
    select EC_GOOGLE_CHROMEEC_SWITCHES
    select VBOOT_LID_SWITCH
diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig
index b04cc46..dac8f3b 100644
--- a/src/mainboard/google/jecht/Kconfig
+++ b/src/mainboard/google/jecht/Kconfig
@@ -14,9 +14,6 @@

if BOARD_GOOGLE_BASEBOARD_JECHT

-config CHROMEOS
-	select CHROMEOS_RAMOOPS_DYNAMIC
-
 config VBOOT
    select VBOOT_VBNV_CMOS

diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig
index 7ac5f1c..6312220 100644
--- a/src/mainboard/intel/wtm2/Kconfig
+++ b/src/mainboard/intel/wtm2/Kconfig
@@ -11,9 +11,6 @@
    select MAINBOARD_HAS_LPC_TPM
    select INTEL_INT15

-config CHROMEOS
-	select CHROMEOS_RAMOOPS_DYNAMIC
-
 config VBOOT
    select VBOOT_VBNV_CMOS

diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 7528c09..bf84f7a 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -73,6 +73,9 @@
      binary is used meaning a jump is made from RW to the RO region
      and back to the RW region after the binary is done.

+config CHROMEOS
+	select CHROMEOS_RAMOOPS_DYNAMIC
+
 config VBOOT
    select VBOOT_MUST_REQUEST_DISPLAY
    select VBOOT_STARTS_IN_ROMSTAGE if !BROADWELL_VBOOT_IN_BOOTBLOCK
diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c
index bc26388..f89552c 100644
--- a/src/soc/intel/broadwell/northbridge.c
+++ b/src/soc/intel/broadwell/northbridge.c
@@ -9,7 +9,6 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 #include <soc/acpi.h>
 #include <soc/iomap.h>
 #include <soc/pci_devs.h>
@@ -372,9 +371,6 @@
    reserved_ram_resource(dev, index++, (0xc0000 >> 10),
    			(0x100000 - 0xc0000) >> 10);

-	if (CONFIG(CHROMEOS))
-		chromeos_reserve_ram_oops(dev, index++);
-
    *resource_cnt = index;
 }