Change in coreboot[master]: soc/amd/cezanne: Enable SOC_AMD_COMMON_BLOCK_SPI

[Raul Rangel (Code Review)]

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50344 )

Change subject: soc/amd/cezanne: Enable SOC_AMD_COMMON_BLOCK_SPI
......................................................................

soc/amd/cezanne: Enable SOC_AMD_COMMON_BLOCK_SPI

Required so we pass SPI information down to depthcharge.

Signed-off-by: Raul E Rangel 
Change-Id: I4ce819b537333c28d394c925331e3dbf260b7732
---
M src/soc/amd/cezanne/Kconfig
1 file changed, 2 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/50344/1

diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 611260d..c37f031 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -13,6 +13,7 @@
    select ARCH_VERSTAGE_X86_32
    select ARCH_ROMSTAGE_X86_32
    select ARCH_RAMSTAGE_X86_32
+	select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
    select FSP_COMPRESS_FSP_M_LZMA
    select FSP_COMPRESS_FSP_S_LZMA
    select HAVE_CF9_RESET
@@ -29,6 +30,7 @@
    select SOC_AMD_COMMON_BLOCK_PSP_GEN2
    select SOC_AMD_COMMON_BLOCK_SMBUS
    select SOC_AMD_COMMON_BLOCK_SMI
+	select SOC_AMD_COMMON_BLOCK_SPI
    select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
    select SOC_AMD_COMMON_BLOCK_UART
    select SSE2