Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85841?usp=email )
Change subject: soc/mediatek/mt8196: Add clk_buf drivers ......................................................................
soc/mediatek/mt8196: Add clk_buf drivers
Mt8196 use mt6685 clk_buf, and will use new RC mode with srclken_rc.
TEST=Build pass. BUG=b:317009620
Signed-off-by: ot_song fan ot_song.fan@mediatek.corp-partner.google.com Change-Id: Ie18bfbb2f3354ba3645799857061dc20de7f6d84 --- M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/clkbuf_ctl.c A src/soc/mediatek/mt8196/include/soc/clkbuf_ctl.h 3 files changed, 971 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/85841/1
diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index e967707..a079a05 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -24,6 +24,7 @@ bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c
romstage-y += ../common/cbmem.c +romstage-y += clkbuf_ctl.c romstage-y += ../common/dram_init.c romstage-y += ../common/dramc_param.c romstage-$(CONFIG_PCI) += ../common/early_init.c ../common/pcie.c diff --git a/src/soc/mediatek/mt8196/clkbuf_ctl.c b/src/soc/mediatek/mt8196/clkbuf_ctl.c new file mode 100644 index 0000000..23a56a7 --- /dev/null +++ b/src/soc/mediatek/mt8196/clkbuf_ctl.c @@ -0,0 +1,430 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <assert.h> +#include <soc/addressmap.h> +#include <soc/clkbuf_ctl.h> +#include <soc/mt6685.h> +#include <timer.h> + +#define XO_RC_MODE 0x1 +#define XO_DISABLE_MODE 0x0 + +#define XO_EN_MODE_MASK 0x7 +#define XO_EN_MODE_SHIFT 0 + +/* Impedance mask/shift, may need update for PMIC which is not 6685*/ +#define XO_IMPEDANCE_MASK 0x7 +#define XO_IMPEDANCE_SHIFT 3 +#define XO_DRIVING_MASK 0x3 +#define XO_DRIVING_SHIFT 6 +#define XO_MODE_SHIFT 0 + +#define clk_buf_enable_xo(xo_id) \ + mt6685_write_field(ox[(xo_id)].reg, \ + XO_RC_MODE, \ + XO_EN_MODE_MASK, \ + XO_MODE_SHIFT) + +#define clk_buf_disable_xo(xo_id) \ + mt6685_write_field(ox[(xo_id)].reg, \ + XO_DISABLE_MODE, \ + XO_EN_MODE_MASK, \ + XO_MODE_SHIFT) + +#define clk_buf_impedance_config(xo_id) \ + mt6685_write_field(ox[(xo_id)].reg, \ + ox[(xo_id)].impedance, \ + XO_IMPEDANCE_MASK, \ + XO_IMPEDANCE_SHIFT) + +#define clk_buf_driving_config(xo_id) \ + mt6685_write_field(ox[(xo_id)].reg, \ + ox[(xo_id)].driving, \ + XO_DRIVING_MASK, \ + XO_DRIVING_SHIFT) + +/* Porting starting from here */ + +/* SPMI master/slave, might change in the future */ +#define CLKBUF_SPMI_MASTER SPMI_MASTER_1 +#define CLKBUF_SPMI_SLAVE SPMI_SLAVE_9 + +/* Voting table */ +#define SOC_VOTER_L_MASK 0x01 +#define SOC_VOTER_H_MASK 0x00 + +#define CONN_PCIE_VOTER_L_MASK 0x80 +#define CONN_PCIE_VOTER_H_MASK 0x02 + +#define CONN_GPS_VOTER_L_MASK 0x40 +#define CONN_GPS_VOTER_H_MASK 0x00 + +#define MMWAVE_VOTER_L_MASK 0x00 +#define MMWAVE_VOTER_H_MASK 0x00 + +#define NFC_VOTER_L_MASK 0x00 +#define NFC_VOTER_H_MASK 0x08 + +#define RFMD_2A_VOTER_L_MASK 0x10 +#define RFMD_2A_VOTER_H_MASK 0x00 + +#define UFS_VOTER_L_MASK 0x00 +#define UFS_VOTER_H_MASK 0x20 + +struct ox_cfg ox[] = { + [XO_BBCK1] = { + .reg = XO_BBCK1_MODE_ADDR, + .mode = BBCK_BUF1_STATUS_PMIC, + .impedance = BBCK_BUF1_OUTPUT_IMPEDANCE, + .driving = BBCK_BUF1_DRIVING_STRENGTH, + .voter_mask = { /* 0x0001 */ + .low_byte = SOC_VOTER_L_MASK, + .high_byte = SOC_VOTER_H_MASK, + }, + }, + [XO_BBCK2] = { + .reg = XO_BBCK2_MODE_ADDR, + .mode = BBCK_BUF2_STATUS_PMIC, + .impedance = BBCK_BUF2_OUTPUT_IMPEDANCE, + .driving = BBCK_BUF2_DRIVING_STRENGTH, + .voter_mask = { /* 0x0280 */ + .low_byte = CONN_PCIE_VOTER_L_MASK, + .high_byte = CONN_PCIE_VOTER_H_MASK, + }, + }, + [XO_BBCK3] = { + .reg = XO_BBCK3_MODE_ADDR, + .mode = BBCK_BUF3_STATUS_PMIC, + .impedance = BBCK_BUF3_OUTPUT_IMPEDANCE, + .driving = BBCK_BUF3_DRIVING_STRENGTH, + .voter_mask = { /* 0x0000 */ + .low_byte = 0x0, + .high_byte = 0x0, + }, + }, + [XO_BBCK4] = { + .reg = XO_BBCK4_MODE_ADDR, + .mode = BBCK_BUF4_STATUS_PMIC, + .impedance = BBCK_BUF4_OUTPUT_IMPEDANCE, + .driving = BBCK_BUF4_DRIVING_STRENGTH, + .voter_mask = { /* 0x0800 */ + .low_byte = NFC_VOTER_L_MASK, + .high_byte = NFC_VOTER_H_MASK, + }, + }, + [XO_BBCK5] = { + .reg = XO_BBCK5_MODE_ADDR, + .mode = BBCK_BUF5_STATUS_PMIC, + .impedance = BBCK_BUF5_OUTPUT_IMPEDANCE, + .driving = BBCK_BUF5_DRIVING_STRENGTH, + .voter_mask = { /* 0x0000 */ + .low_byte = 0x0, + .high_byte = 0x0, + }, + }, + [XO_RFCK1A] = { + .reg = XO_RFCK1A_MODE_ADDR, + .mode = RFCK_BUF1A_STATUS_PMIC, + .impedance = RFCK_BUF1A_OUTPUT_IMPEDANCE, + .driving = 0, + .voter_mask = { /* 0x0000 */ + .low_byte = MMWAVE_VOTER_L_MASK, + .high_byte = MMWAVE_VOTER_H_MASK, + }, + }, + [XO_RFCK1B] = { + .reg = XO_RFCK1B_MODE_ADDR, + .mode = RFCK_BUF1B_STATUS_PMIC, + .impedance = RFCK_BUF1B_OUTPUT_IMPEDANCE, + .driving = 0, + .voter_mask = { /* 0x2000 */ + .low_byte = UFS_VOTER_L_MASK, + .high_byte = UFS_VOTER_H_MASK, + }, + }, + [XO_RFCK1C] = { + .reg = XO_RFCK1C_MODE_ADDR, + .mode = CLOCK_BUFFER_DISABLE, + .impedance = 0, + .driving = 0, + .voter_mask = { + .low_byte = 0x0, + .high_byte = 0x0, + }, + }, + [XO_RFCK2A] = { + .reg = XO_RFCK2A_MODE_ADDR, + .mode = RFCK_BUF2A_STATUS_PMIC, + .impedance = RFCK_BUF2A_OUTPUT_IMPEDANCE, + .driving = 0, + .voter_mask = { /* 0x0010 */ + .low_byte = RFMD_2A_VOTER_L_MASK, + .high_byte = RFMD_2A_VOTER_H_MASK, + }, + }, + [XO_RFCK2B] = { + .reg = XO_RFCK2B_MODE_ADDR, + .mode = RFCK_BUF2B_STATUS_PMIC, + .impedance = RFCK_BUF2B_OUTPUT_IMPEDANCE, + .driving = 0, + .voter_mask = { /* 0x0040 */ + .low_byte = CONN_GPS_VOTER_L_MASK, + .high_byte = CONN_GPS_VOTER_H_MASK, + }, + }, + [XO_RFCK2C] = { + .reg = XO_RFCK2C_MODE_ADDR, + .mode = CLOCK_BUFFER_DISABLE, + .impedance = 0, + .driving = 0, + .voter_mask = { + .low_byte = 0x0, + .high_byte = 0x0, + }, + }, + [XO_CONCK1] = { + .reg = XO_CONCK1_MODE_ADDR, + .mode = CLOCK_BUFFER_DISABLE, + .impedance = 0, + .driving = 0, + .voter_mask = { + .low_byte = 0x0, + .high_byte = 0x0, + }, + }, + [XO_CONCK2] = { + .reg = XO_CONCK2_MODE_ADDR, + .mode = CLOCK_BUFFER_DISABLE, + .impedance = 0, + .driving = 0, + .voter_mask = { + .low_byte = 0x0, + .high_byte = 0x0, + }, + } +}; + +unsigned int clk_buf_get_pmrc_en0(void) +{ + unsigned int out = 0; + unsigned char tmp = 0; + + tmp = mt6685_read8(MT6685_PMRC_CON0); + out = tmp; + tmp = mt6685_read8(MT6685_PMRC_CON1); + out |= tmp << 8; + + return out; +} + +static void clk_buf_dump_dws_log(void) +{ + u8 i; + + printk(BIOS_INFO, "%s: DWS_CLKBUF_STA BBCK1/2/3/4/5=", __func__); + for (i = XO_BBCK1; i <= XO_BBCK5; ++i) + printk(BIOS_INFO, "%u/", ox[i].mode); + + printk(BIOS_INFO, "\nRFCK1A/1B/1C/2A/2B/2C="); + for (i = XO_RFCK1A; i <= XO_RFCK2C; ++i) + printk(BIOS_INFO, "%u/", ox[i].mode); + + printk(BIOS_INFO, "\nCONCK1/2="); + for (i = XO_CONCK1; i <= XO_CONCK2; ++i) + printk(BIOS_INFO, "%u/", ox[i].mode); + + printk(BIOS_INFO, "\n"); + + + printk(BIOS_INFO, "%s: DWS_CLK_BUF_IMPEDANCE BBCK1/2/3/4/5=", __func__); + for (i = XO_BBCK1; i <= XO_BBCK5; ++i) + printk(BIOS_INFO, "%u/", ox[i].impedance); + + printk(BIOS_INFO, "\nRFCK1A/1B/1C/2A/2B/2C="); + for (i = XO_RFCK1A; i <= XO_RFCK2C; ++i) + printk(BIOS_INFO, "%u/", ox[i].impedance); + + printk(BIOS_INFO, "\nCONCK1/2="); + for (i = XO_CONCK1; i <= XO_CONCK2; ++i) + printk(BIOS_INFO, "%u/", ox[i].impedance); + + printk(BIOS_INFO, "\n"); + + printk(BIOS_INFO, "%s: DWS_CLK_BUF_DRIVING BBCK1/2/3/4/5=", __func__); + for (i = XO_BBCK1; i <= XO_BBCK5; ++i) + printk(BIOS_INFO, "%u/", ox[i].driving); + + printk(BIOS_INFO, "\n"); +} + +static void clk_buf_dump_clkbuf_log(void) +{ + u8 val; + u8 xo_buf_cw[XO_NUMBER]; + u16 xo_buf_vote[XO_NUMBER]; + u8 dig_manctrl_cw1; + u8 bblpm_cw0; + u32 dig26m_div2; + u8 i; + + for (i = 0; i < XO_NUMBER; i++) { + xo_buf_cw[i] = mt6685_read8(MT6685_DCXO_EXTBUF1_CW0 + i); + val = mt6685_read8(MT6685_XO_BUF_CTL0_L + (2 * i)); + xo_buf_vote[i] = val; + + val = mt6685_read8(MT6685_XO_BUF_CTL0_H + (2 * i)); + xo_buf_vote[i] |= (val << 8); + } + + dig_manctrl_cw1 = mt6685_read8(MT6685_DCXO_DIG_MANCTRL_CW1); + bblpm_cw0 = mt6685_read8(MT6685_DCXO_BBLPM_CW0); + + dig26m_div2 = mt6685_read_field(RG_XO_DIG26M_DIV2_ADDR, + RG_XO_DIG26M_DIV2_MASK, + RG_XO_DIG26M_DIV2_SHIFT); + + printk(BIOS_INFO, "%s: xo_buf_cw(0x79A ~ 0x7A6):\n", __func__); + for (i = 0; i < XO_NUMBER; ++i) + printk(BIOS_INFO, "0x%x/", xo_buf_cw[i]); + printk(BIOS_INFO, "\n"); + + printk(BIOS_INFO, "%s: xo_buf_vote(0x54C ~ 0x565):\n", __func__); + for (i = 0; i < XO_NUMBER; ++i) + printk(BIOS_INFO, "0x%x/", xo_buf_vote[i]); + printk(BIOS_INFO, "\n"); + + printk(BIOS_INFO, "%s: dig_manctrl_cw1(0x%x): 0x%x\nbblpm_cw0(0x%x): 0x%x\n", + __func__, + MT6685_DCXO_DIG_MANCTRL_CW1, + dig_manctrl_cw1, + MT6685_DCXO_BBLPM_CW0, + bblpm_cw0); + printk(BIOS_INFO, "%s: dig26m_div2(0x%x): 0x%x\n", + __func__, + RG_XO_DIG26M_DIV2_ADDR, + dig26m_div2); +} + +static void clk_buf_init_pmic_clkbuf(void) +{ + u8 val; + u8 i; + + /* 1.1 Write XO_BUF impedance & driving */ + for (i = 0; i < XO_NUMBER; ++i) + if (ox[i].mode != CLOCK_BUFFER_DISABLE) + clk_buf_impedance_config(i); + + /* 1.2 Write XO_BUF driving */ + for (i = 0; i <= XO_BBCK5; ++i) + if (ox[i].mode != CLOCK_BUFFER_DISABLE) + clk_buf_driving_config(i); + + /* 1.3 Mask RC voting table by dws */ + for (i = 0; i < XO_NUMBER; ++i) { + if (ox[i].mode == CLOCK_BUFFER_DISABLE) { + ox[i].voter_mask.low_byte = 0; + ox[i].voter_mask.high_byte = 0; + } + } + + /* 1.4 Write RC voting table */ + for (i = 0; i < XO_NUMBER; i++) { + mt6685_write8(XO_BBCK1_VOTE_L_ADDR + (2 * i), + ox[i].voter_mask.low_byte); + mt6685_write8(XO_BBCK1_VOTE_H_ADDR + (2 * i), + ox[i].voter_mask.high_byte); + } + + /* 1.5 turn on LDO HW control from XO_BUFs */ + mt6685_write_field(RG_LDO_VRFCK1_HW14_OP_EN_ADDR, + 0x1, + RG_LDO_VRFCK1_HW14_OP_EN_MASK, + RG_LDO_VRFCK1_HW14_OP_EN_SHIFT); + + mt6685_write_field(RG_LDO_VRFCK2_HW14_OP_EN_ADDR, + 0x1, + RG_LDO_VRFCK2_HW14_OP_EN_MASK, + RG_LDO_VRFCK2_HW14_OP_EN_SHIFT); + + mt6685_write_field(RG_LDO_VBBCK_HW14_OP_EN_ADDR, + 0x1, + RG_LDO_VBBCK_HW14_OP_EN_MASK, + RG_LDO_VBBCK_HW14_OP_EN_SHIFT); + + /* 1.6 turn off LDO SW control */ + mt6685_write_field(RG_LDO_VRFCK1_EN_ADDR, + 0x0, + RG_LDO_VRFCK1_EN_MASK, + RG_LDO_VRFCK1_EN_SHIFT); + + mt6685_write_field(RG_LDO_VRFCK2_EN_ADDR, + 0x0, + RG_LDO_VRFCK2_EN_MASK, + RG_LDO_VRFCK2_EN_SHIFT); + + mt6685_write_field(RG_LDO_VBBCK_EN_ADDR, + 0x0, + RG_LDO_VBBCK_EN_MASK, + RG_LDO_VBBCK_EN_SHIFT); + + /* 1.7 Enable/Disable XO by dws */ + for (i = 0; i < XO_NUMBER; ++i) { + if (ox[i].mode == CLOCK_BUFFER_DISABLE || + ox[i].mode == CLOCK_BUFFER_SW_CONTROL) + clk_buf_disable_xo(i); + else if (ox[i].mode == CLOCK_BUFFER_HW_CONTROL) + clk_buf_enable_xo(i); + } + + /* 1.8 RC mode setting + * en_bb hw mode + * switch to srclken_rc mode + */ + val = mt6685_read8(MT6685_DCXO_DIG_MANCTRL_CW1); + val &= (~(XO_PMIC_TOP_DIG_SW_MASK << XO_PMIC_TOP_DIG_SW_SHIFT)); + val &= (~(XO_ENBB_MAN_MASK << XO_ENBB_MAN_SHIFT)); + val &= (~(XO_ENBB_EN_M_MASK << XO_ENBB_EN_M_SHIFT)); + val &= (~(XO_CLKSEL_EN_M_MASK << XO_CLKSEL_EN_M_SHIFT)); + mt6685_write8(MT6685_DCXO_DIG_MANCTRL_CW1, val); +} + +static u16 dcxo_dbg_read_auxout(u8 sel) +{ + u16 val = 0; + u8 tmp = 0; + + mt6685_write8(XO_STATIC_AUXOUT_SEL_ADDR, sel); + + tmp = mt6685_read8(XO_STATIC_AUXOUT_L_ADDR); + val = tmp; + + tmp = mt6685_read8(XO_STATIC_AUXOUT_H_ADDR); + val |= tmp << 8; + + printk(BIOS_INFO, "%s: sel=%d, rg_auxout=0x%x\n", + __func__, sel, val); + + return val; +} + +int clk_buf_init(void) +{ + _Static_assert(ARRAY_SIZE(ox) == XO_NUMBER, "Wrong array size of ox"); + + /* Check dws setting */ + clk_buf_dump_dws_log(); + + /* dump lpsd dbg0-3 for debug during pmic_long_press_reset */ + dcxo_dbg_read_auxout(124); + dcxo_dbg_read_auxout(125); + dcxo_dbg_read_auxout(126); + dcxo_dbg_read_auxout(127); + + clk_buf_init_pmic_clkbuf(); + + /* Check if the setting is ok */ + clk_buf_dump_clkbuf_log(); + + return 0; +} diff --git a/src/soc/mediatek/mt8196/include/soc/clkbuf_ctl.h b/src/soc/mediatek/mt8196/include/soc/clkbuf_ctl.h new file mode 100644 index 0000000..94bdaae --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/clkbuf_ctl.h @@ -0,0 +1,540 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __SOC_MEDIATEK_MT8196_INCLUDE_SOC_CLK_BUF_CTL_H__ +#define __SOC_MEDIATEK_MT8196_INCLUDE_SOC_CLK_BUF_CTL_H__ + +#include <console/console.h> + +#define MT6685_PMRC_CON0 0x190 +#define MT6685_PMRC_CON1 0x191 +#define MT6685_PMRC_CON0_SET 0x198 +#define MT6685_PMRC_CON1_SET 0x199 +#define MT6685_PMRC_CON0_CLR 0x19a +#define MT6685_PMRC_CON1_CLR 0x19b +#define MT6685_PMRC_CON3 0x19c +#define MT6685_XO_BUF_CTL0_L 0x54c +#define MT6685_XO_BUF_CTL0_H 0x54d +#define MT6685_XO_BUF_CTL1_L 0x54e +#define MT6685_XO_BUF_CTL1_H 0x54f +#define MT6685_XO_BUF_CTL2_L 0x550 +#define MT6685_XO_BUF_CTL2_H 0x551 +#define MT6685_XO_BUF_CTL3_L 0x552 +#define MT6685_XO_BUF_CTL3_H 0x553 +#define MT6685_XO_BUF_CTL4_L 0x554 +#define MT6685_XO_BUF_CTL4_H 0x555 +#define MT6685_XO_BUF_CTL5_L 0x556 +#define MT6685_XO_BUF_CTL5_H 0x557 +#define MT6685_XO_BUF_CTL6_L 0x558 +#define MT6685_XO_BUF_CTL6_H 0x559 +#define MT6685_XO_BUF_CTL7_L 0x55a +#define MT6685_XO_BUF_CTL7_H 0x55b +#define MT6685_XO_BUF_CTL8_L 0x55c +#define MT6685_XO_BUF_CTL8_H 0x55d +#define MT6685_XO_BUF_CTL9_L 0x55e +#define MT6685_XO_BUF_CTL9_H 0x55f +#define MT6685_XO_BUF_CTL10_L 0x560 +#define MT6685_XO_BUF_CTL10_H 0x561 +#define MT6685_XO_BUF_CTL11_L 0x562 +#define MT6685_XO_BUF_CTL11_H 0x563 +#define MT6685_XO_BUF_CTL12_L 0x564 +#define MT6685_XO_BUF_CTL12_H 0x565 +#define MT6685_XO_CONN_BT0 0x567 +#define MT6685_DCXO_DIG_MANCTRL_CW1 0x796 +#define MT6685_DCXO_BBLPM_CW0 0x797 +#define MT6685_DCXO_BBLPM_CW1 0x798 +#define MT6685_DCXO_LDO_CW0 0x799 +#define MT6685_DCXO_EXTBUF1_CW0 0x79a +#define MT6685_DCXO_EXTBUF2_CW0 0x79b +#define MT6685_DCXO_EXTBUF3_CW0 0x79c +#define MT6685_DCXO_EXTBUF4_CW0 0x79d +#define MT6685_DCXO_EXTBUF5_CW0 0x79e +#define MT6685_DCXO_EXTBUF6_CW0 0x79f +#define MT6685_DCXO_EXTBUF7_CW0 0x7a0 +#define MT6685_DCXO_EXTBUF8_CW0 0x7a1 +#define MT6685_DCXO_EXTBUF9_CW0 0x7a2 +#define MT6685_DCXO_EXTBUF10_CW0 0x7a3 +#define MT6685_DCXO_EXTBUF11_CW0 0x7a4 +#define MT6685_DCXO_EXTBUF12_CW0 0x7a5 +#define MT6685_DCXO_EXTBUF13_CW0 0x7a6 +#define MT6685_DCXO_RGMON_CW0_L 0x7b2 +#define MT6685_DCXO_RGMON_CW0_H 0x7b3 +#define MT6685_DCXO_RGMON_CW2_L 0x7b4 +#define MT6685_DCXO_RGMON_CW2_H 0x7b5 +#define MT6685_DCXO_RGMON_CW1 0x7c3 +#define MT6685_DCXO_DIGCLK_ELR 0x7f4 +#define MT6685_LDO_VBBCK_CON0 0x1b87 +#define MT6685_LDO_VBBCK_OP_EN1 0x1b8e +#define MT6685_LDO_VBBCK_OP_EN1_SET 0x1b8f +#define MT6685_LDO_VBBCK_OP_EN1_CLR 0x1b90 +#define MT6685_LDO_VRFCK1_CON0 0x1b97 +#define MT6685_LDO_VRFCK1_OP_EN1 0x1b9e +#define MT6685_LDO_VRFCK1_OP_EN1_SET 0x1b9f +#define MT6685_LDO_VRFCK1_OP_EN1_CLR 0x1ba0 +#define MT6685_LDO_VRFCK2_CON0 0x1ba7 +#define MT6685_LDO_VRFCK2_OP_EN1 0x1bae +#define MT6685_LDO_VRFCK2_OP_EN1_SET 0x1baf +#define MT6685_LDO_VRFCK2_OP_EN1_CLR 0x1bb0 + +/* Register_TOP_REG*/ +#define RG_DCXO_SRCLKEN1_MODE_ADDR MT6685_PMRC_CON3 +#define RG_DCXO_SRCLKEN1_MODE_MASK 0x3 +#define RG_DCXO_SRCLKEN1_MODE_SHIFT 2 +/* Register_SCK_REG*/ +#define XO_BBCK1_VOTE_L_ADDR MT6685_XO_BUF_CTL0_L +#define XO_BBCK1_VOTE_L_MASK 0xff +#define XO_BBCK1_VOTE_L_SHIFT 0 +#define XO_BBCK1_VOTE_H_ADDR MT6685_XO_BUF_CTL0_H +#define XO_BBCK1_VOTE_H_MASK 0x3f +#define XO_BBCK1_VOTE_H_SHIFT 0 +#define XO_BBCK2_VOTE_L_ADDR MT6685_XO_BUF_CTL1_L +#define XO_BBCK2_VOTE_L_MASK 0xff +#define XO_BBCK2_VOTE_L_SHIFT 0 +#define XO_BBCK2_VOTE_H_ADDR MT6685_XO_BUF_CTL1_H +#define XO_BBCK2_VOTE_H_MASK 0x3f +#define XO_BBCK2_VOTE_H_SHIFT 0 +#define XO_BBCK3_VOTE_L_ADDR MT6685_XO_BUF_CTL2_L +#define XO_BBCK3_VOTE_L_MASK 0xff +#define XO_BBCK3_VOTE_L_SHIFT 0 +#define XO_BBCK3_VOTE_H_ADDR MT6685_XO_BUF_CTL2_H +#define XO_BBCK3_VOTE_H_MASK 0x3f +#define XO_BBCK3_VOTE_H_SHIFT 0 +#define XO_BBCK4_VOTE_L_ADDR MT6685_XO_BUF_CTL3_L +#define XO_BBCK4_VOTE_L_MASK 0xff +#define XO_BBCK4_VOTE_L_SHIFT 0 +#define XO_BBCK4_VOTE_H_ADDR MT6685_XO_BUF_CTL3_H +#define XO_BBCK4_VOTE_H_MASK 0x3f +#define XO_BBCK4_VOTE_H_SHIFT 0 +#define XO_BBCK5_VOTE_L_ADDR MT6685_XO_BUF_CTL4_L +#define XO_BBCK5_VOTE_L_MASK 0xff +#define XO_BBCK5_VOTE_L_SHIFT 0 +#define XO_BBCK5_VOTE_H_ADDR MT6685_XO_BUF_CTL4_H +#define XO_BBCK5_VOTE_H_MASK 0x3f +#define XO_BBCK5_VOTE_H_SHIFT 0 +#define XO_RFCK1A_VOTE_L_ADDR MT6685_XO_BUF_CTL5_L +#define XO_RFCK1A_VOTE_L_MASK 0xff +#define XO_RFCK1A_VOTE_L_SHIFT 0 +#define XO_RFCK1A_VOTE_H_ADDR MT6685_XO_BUF_CTL5_H +#define XO_RFCK1A_VOTE_H_MASK 0x3f +#define XO_RFCK1A_VOTE_H_SHIFT 0 +#define XO_RFCK1B_VOTE_L_ADDR MT6685_XO_BUF_CTL6_L +#define XO_RFCK1B_VOTE_L_MASK 0xff +#define XO_RFCK1B_VOTE_L_SHIFT 0 +#define XO_RFCK1B_VOTE_H_ADDR MT6685_XO_BUF_CTL6_H +#define XO_RFCK1B_VOTE_H_MASK 0x3f +#define XO_RFCK1B_VOTE_H_SHIFT 0 +#define XO_RFCK1C_VOTE_L_ADDR MT6685_XO_BUF_CTL7_L +#define XO_RFCK1C_VOTE_L_MASK 0xff +#define XO_RFCK1C_VOTE_L_SHIFT 0 +#define XO_RFCK1C_VOTE_H_ADDR MT6685_XO_BUF_CTL7_H +#define XO_RFCK1C_VOTE_H_MASK 0x3f +#define XO_RFCK1C_VOTE_H_SHIFT 0 +#define XO_RFCK2A_VOTE_L_ADDR MT6685_XO_BUF_CTL8_L +#define XO_RFCK2A_VOTE_L_MASK 0xff +#define XO_RFCK2A_VOTE_L_SHIFT 0 +#define XO_RFCK2A_VOTE_H_ADDR MT6685_XO_BUF_CTL8_H +#define XO_RFCK2A_VOTE_H_MASK 0x3f +#define XO_RFCK2A_VOTE_H_SHIFT 0 +#define XO_RFCK2B_VOTE_L_ADDR MT6685_XO_BUF_CTL9_L +#define XO_RFCK2B_VOTE_L_MASK 0xff +#define XO_RFCK2B_VOTE_L_SHIFT 0 +#define XO_RFCK2B_VOTE_H_ADDR MT6685_XO_BUF_CTL9_H +#define XO_RFCK2B_VOTE_H_MASK 0x3f +#define XO_RFCK2B_VOTE_H_SHIFT 0 +#define XO_RFCK2C_VOTE_L_ADDR MT6685_XO_BUF_CTL10_L +#define XO_RFCK2C_VOTE_L_MASK 0xff +#define XO_RFCK2C_VOTE_L_SHIFT 0 +#define XO_RFCK2C_VOTE_H_ADDR MT6685_XO_BUF_CTL10_H +#define XO_RFCK2C_VOTE_H_MASK 0x3f +#define XO_RFCK2C_VOTE_H_SHIFT 0 +#define XO_CONCK1_VOTE_L_ADDR MT6685_XO_BUF_CTL11_L +#define XO_CONCK1_VOTE_L_MASK 0xff +#define XO_CONCK1_VOTE_L_SHIFT 0 +#define XO_CONCK1_VOTE_H_ADDR MT6685_XO_BUF_CTL11_H +#define XO_CONCK1_VOTE_H_MASK 0x3f +#define XO_CONCK1_VOTE_H_SHIFT 0 +#define XO_CONCK2_VOTE_L_ADDR MT6685_XO_BUF_CTL12_L +#define XO_CONCK2_VOTE_L_MASK 0xff +#define XO_CONCK2_VOTE_L_SHIFT 0 +#define XO_CONCK2_VOTE_H_ADDR MT6685_XO_BUF_CTL12_H +#define XO_CONCK2_VOTE_H_MASK 0x3f +#define XO_CONCK2_VOTE_H_SHIFT 0 +#define XO_MODE_CONN_BT_MASK_ADDR MT6685_XO_CONN_BT0 +#define XO_MODE_CONN_BT_MASK_MASK 0x1 +#define XO_MODE_CONN_BT_MASK_SHIFT 0 +#define XO_BUF_CONN_BT_MASK_ADDR MT6685_XO_CONN_BT0 +#define XO_BUF_CONN_BT_MASK_MASK 0x1 +#define XO_BUF_CONN_BT_MASK_SHIFT 1 +/* Register_DCXO_REG*/ +#define XO_PMIC_TOP_DIG_SW_ADDR MT6685_DCXO_DIG_MANCTRL_CW1 +#define XO_PMIC_TOP_DIG_SW_MASK 0x1 +#define XO_PMIC_TOP_DIG_SW_SHIFT 0 +#define XO_ENBB_MAN_ADDR MT6685_DCXO_DIG_MANCTRL_CW1 +#define XO_ENBB_MAN_MASK 0x1 +#define XO_ENBB_MAN_SHIFT 1 +#define XO_ENBB_EN_M_ADDR MT6685_DCXO_DIG_MANCTRL_CW1 +#define XO_ENBB_EN_M_MASK 0x1 +#define XO_ENBB_EN_M_SHIFT 2 +#define XO_CLKSEL_MAN_ADDR MT6685_DCXO_DIG_MANCTRL_CW1 +#define XO_CLKSEL_MAN_MASK 0x1 +#define XO_CLKSEL_MAN_SHIFT 3 +#define XO_CLKSEL_EN_M_ADDR MT6685_DCXO_DIG_MANCTRL_CW1 +#define XO_CLKSEL_EN_M_MASK 0x1 +#define XO_CLKSEL_EN_M_SHIFT 4 +#define XO_BB_LPM_EN_M_ADDR MT6685_DCXO_BBLPM_CW0 +#define XO_BB_LPM_EN_M_MASK 0x1 +#define XO_BB_LPM_EN_M_SHIFT 0 +#define XO_BB_LPM_EN_SEL_ADDR MT6685_DCXO_BBLPM_CW0 +#define XO_BB_LPM_EN_SEL_MASK 0x1 +#define XO_BB_LPM_EN_SEL_SHIFT 1 +#define XO_BBCK1_BBLPM_EN_MASK_ADDR MT6685_DCXO_BBLPM_CW0 +#define XO_BBCK1_BBLPM_EN_MASK_MASK 0x1 +#define XO_BBCK1_BBLPM_EN_MASK_SHIFT 2 +#define XO_BBCK2_BBLPM_EN_MASK_ADDR MT6685_DCXO_BBLPM_CW0 +#define XO_BBCK2_BBLPM_EN_MASK_MASK 0x1 +#define XO_BBCK2_BBLPM_EN_MASK_SHIFT 3 +#define XO_BBCK3_BBLPM_EN_MASK_ADDR MT6685_DCXO_BBLPM_CW0 +#define XO_BBCK3_BBLPM_EN_MASK_MASK 0x1 +#define XO_BBCK3_BBLPM_EN_MASK_SHIFT 4 +#define XO_BBCK4_BBLPM_EN_MASK_ADDR MT6685_DCXO_BBLPM_CW0 +#define XO_BBCK4_BBLPM_EN_MASK_MASK 0x1 +#define XO_BBCK4_BBLPM_EN_MASK_SHIFT 5 +#define XO_BBCK5_BBLPM_EN_MASK_ADDR MT6685_DCXO_BBLPM_CW0 +#define XO_BBCK5_BBLPM_EN_MASK_MASK 0x1 +#define XO_BBCK5_BBLPM_EN_MASK_SHIFT 6 +#define XO_BBLPM_EN_MAN_ADDR MT6685_DCXO_BBLPM_CW1 +#define XO_BBLPM_EN_MAN_MASK 0x1 +#define XO_BBLPM_EN_MAN_SHIFT 0 +#define XO_BBLPM_EN_MAN_M_ADDR MT6685_DCXO_BBLPM_CW1 +#define XO_BBLPM_EN_MAN_M_MASK 0x1 +#define XO_BBLPM_EN_MAN_M_SHIFT 1 +#define XO_VBBCK_EN_MAN_ADDR MT6685_DCXO_LDO_CW0 +#define XO_VBBCK_EN_MAN_MASK 0x1 +#define XO_VBBCK_EN_MAN_SHIFT 0 +#define XO_VBBCK_EN_M_ADDR MT6685_DCXO_LDO_CW0 +#define XO_VBBCK_EN_M_MASK 0x1 +#define XO_VBBCK_EN_M_SHIFT 1 +#define XO_VRFCK1_EN_MAN_ADDR MT6685_DCXO_LDO_CW0 +#define XO_VRFCK1_EN_MAN_MASK 0x1 +#define XO_VRFCK1_EN_MAN_SHIFT 2 +#define XO_VRFCK1_EN_M_ADDR MT6685_DCXO_LDO_CW0 +#define XO_VRFCK1_EN_M_MASK 0x1 +#define XO_VRFCK1_EN_M_SHIFT 3 +#define XO_VRFCK2_EN_MAN_ADDR MT6685_DCXO_LDO_CW0 +#define XO_VRFCK2_EN_MAN_MASK 0x1 +#define XO_VRFCK2_EN_MAN_SHIFT 4 +#define XO_VRFCK2_EN_M_ADDR MT6685_DCXO_LDO_CW0 +#define XO_VRFCK2_EN_M_MASK 0x1 +#define XO_VRFCK2_EN_M_SHIFT 5 +#define XO_VCONCK_EN_MAN_ADDR MT6685_DCXO_LDO_CW0 +#define XO_VCONCK_EN_MAN_MASK 0x1 +#define XO_VCONCK_EN_MAN_SHIFT 6 +#define XO_VCONCK_EN_M_ADDR MT6685_DCXO_LDO_CW0 +#define XO_VCONCK_EN_M_MASK 0x1 +#define XO_VCONCK_EN_M_SHIFT 7 +#define XO_BBCK1_MODE_ADDR MT6685_DCXO_EXTBUF1_CW0 +#define XO_BBCK1_EN_M_ADDR MT6685_DCXO_EXTBUF1_CW0 +#define XO_BBCK1_EN_M_MASK 0x1 +#define XO_BBCK1_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_BBCK1_RSEL_ADDR MT6685_DCXO_EXTBUF1_CW0 +#define RG_XO_EXTBUF_BBCK1_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_BBCK1_RSEL_SHIFT 3 +#define RG_XO_EXTBUF_BBCK1_HD_ADDR MT6685_DCXO_EXTBUF1_CW0 +#define RG_XO_EXTBUF_BBCK1_HD_MASK 0x3 +#define RG_XO_EXTBUF_BBCK1_HD_SHIFT 6 +#define XO_BBCK2_MODE_ADDR MT6685_DCXO_EXTBUF2_CW0 +#define XO_BBCK2_EN_M_ADDR MT6685_DCXO_EXTBUF2_CW0 +#define XO_BBCK2_EN_M_MASK 0x1 +#define XO_BBCK2_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_BBCK2_RSEL_ADDR MT6685_DCXO_EXTBUF2_CW0 +#define RG_XO_EXTBUF_BBCK2_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_BBCK2_RSEL_SHIFT 3 +#define RG_XO_EXTBUF_BBCK2_HD_ADDR MT6685_DCXO_EXTBUF2_CW0 +#define RG_XO_EXTBUF_BBCK2_HD_MASK 0x3 +#define RG_XO_EXTBUF_BBCK2_HD_SHIFT 6 +#define XO_BBCK3_MODE_ADDR MT6685_DCXO_EXTBUF3_CW0 +#define XO_BBCK3_EN_M_ADDR MT6685_DCXO_EXTBUF3_CW0 +#define XO_BBCK3_EN_M_MASK 0x1 +#define XO_BBCK3_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_BBCK3_RSEL_ADDR MT6685_DCXO_EXTBUF3_CW0 +#define RG_XO_EXTBUF_BBCK3_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_BBCK3_RSEL_SHIFT 3 +#define RG_XO_EXTBUF_BBCK3_HD_ADDR MT6685_DCXO_EXTBUF3_CW0 +#define RG_XO_EXTBUF_BBCK3_HD_MASK 0x3 +#define RG_XO_EXTBUF_BBCK3_HD_SHIFT 6 +#define XO_BBCK4_MODE_ADDR MT6685_DCXO_EXTBUF4_CW0 +#define XO_BBCK4_EN_M_ADDR MT6685_DCXO_EXTBUF4_CW0 +#define XO_BBCK4_EN_M_MASK 0x1 +#define XO_BBCK4_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_BBCK4_RSEL_ADDR MT6685_DCXO_EXTBUF4_CW0 +#define RG_XO_EXTBUF_BBCK4_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_BBCK4_RSEL_SHIFT 3 +#define RG_XO_EXTBUF_BBCK4_HD_ADDR MT6685_DCXO_EXTBUF4_CW0 +#define RG_XO_EXTBUF_BBCK4_HD_MASK 0x3 +#define RG_XO_EXTBUF_BBCK4_HD_SHIFT 6 +#define XO_BBCK5_MODE_ADDR MT6685_DCXO_EXTBUF5_CW0 +#define XO_BBCK5_EN_M_ADDR MT6685_DCXO_EXTBUF5_CW0 +#define XO_BBCK5_EN_M_MASK 0x1 +#define XO_BBCK5_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_BBCK5_RSEL_ADDR MT6685_DCXO_EXTBUF5_CW0 +#define RG_XO_EXTBUF_BBCK5_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_BBCK5_RSEL_SHIFT 3 +#define RG_XO_EXTBUF_BBCK5_HD_ADDR MT6685_DCXO_EXTBUF5_CW0 +#define RG_XO_EXTBUF_BBCK5_HD_MASK 0x3 +#define RG_XO_EXTBUF_BBCK5_HD_SHIFT 6 +#define XO_RFCK1A_MODE_ADDR MT6685_DCXO_EXTBUF6_CW0 +#define XO_RFCK1A_EN_M_ADDR MT6685_DCXO_EXTBUF6_CW0 +#define XO_RFCK1A_EN_M_MASK 0x1 +#define XO_RFCK1A_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_RFCK1A_RSEL_ADDR MT6685_DCXO_EXTBUF6_CW0 +#define RG_XO_EXTBUF_RFCK1A_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_RFCK1A_RSEL_SHIFT 3 +#define XO_RFCK1B_MODE_ADDR MT6685_DCXO_EXTBUF7_CW0 +#define XO_RFCK1B_EN_M_ADDR MT6685_DCXO_EXTBUF7_CW0 +#define XO_RFCK1B_EN_M_MASK 0x1 +#define XO_RFCK1B_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_RFCK1B_RSEL_ADDR MT6685_DCXO_EXTBUF7_CW0 +#define RG_XO_EXTBUF_RFCK1B_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_RFCK1B_RSEL_SHIFT 3 +#define XO_RFCK1C_MODE_ADDR MT6685_DCXO_EXTBUF8_CW0 +#define XO_RFCK1C_EN_M_ADDR MT6685_DCXO_EXTBUF8_CW0 +#define XO_RFCK1C_EN_M_MASK 0x1 +#define XO_RFCK1C_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_RFCK1C_RSEL_ADDR MT6685_DCXO_EXTBUF8_CW0 +#define RG_XO_EXTBUF_RFCK1C_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_RFCK1C_RSEL_SHIFT 3 +#define XO_RFCK2A_MODE_ADDR MT6685_DCXO_EXTBUF9_CW0 +#define XO_RFCK2A_EN_M_ADDR MT6685_DCXO_EXTBUF9_CW0 +#define XO_RFCK2A_EN_M_MASK 0x1 +#define XO_RFCK2A_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_RFCK2A_RSEL_ADDR MT6685_DCXO_EXTBUF9_CW0 +#define RG_XO_EXTBUF_RFCK2A_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_RFCK2A_RSEL_SHIFT 3 +#define XO_RFCK2B_MODE_ADDR MT6685_DCXO_EXTBUF10_CW0 +#define XO_RFCK2B_EN_M_ADDR MT6685_DCXO_EXTBUF10_CW0 +#define XO_RFCK2B_EN_M_MASK 0x1 +#define XO_RFCK2B_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_RFCK2B_RSEL_ADDR MT6685_DCXO_EXTBUF10_CW0 +#define RG_XO_EXTBUF_RFCK2B_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_RFCK2B_RSEL_SHIFT 3 +#define XO_RFCK2C_MODE_ADDR MT6685_DCXO_EXTBUF11_CW0 +#define XO_RFCK2C_EN_M_ADDR MT6685_DCXO_EXTBUF11_CW0 +#define XO_RFCK2C_EN_M_MASK 0x1 +#define XO_RFCK2C_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_RFCK2C_RSEL_ADDR MT6685_DCXO_EXTBUF11_CW0 +#define RG_XO_EXTBUF_RFCK2C_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_RFCK2C_RSEL_SHIFT 3 +#define XO_CONCK1_MODE_ADDR MT6685_DCXO_EXTBUF12_CW0 +#define XO_CONCK1_EN_M_ADDR MT6685_DCXO_EXTBUF12_CW0 +#define XO_CONCK1_EN_M_MASK 0x1 +#define XO_CONCK1_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_CONCK1_RSEL_ADDR MT6685_DCXO_EXTBUF12_CW0 +#define RG_XO_EXTBUF_CONCK1_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_CONCK1_RSEL_SHIFT 3 +#define XO_CONCK2_MODE_ADDR MT6685_DCXO_EXTBUF13_CW0 +#define XO_CONCK2_EN_M_ADDR MT6685_DCXO_EXTBUF13_CW0 +#define XO_CONCK2_EN_M_MASK 0x1 +#define XO_CONCK2_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_CONCK2_RSEL_ADDR MT6685_DCXO_EXTBUF13_CW0 +#define RG_XO_EXTBUF_CONCK2_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_CONCK2_RSEL_SHIFT 3 +#define XO_AUXOUT_SEL_L_ADDR MT6685_DCXO_RGMON_CW0_L +#define XO_AUXOUT_SEL_L_MASK 0xff +#define XO_AUXOUT_SEL_L_SHIFT 0 +#define XO_AUXOUT_SEL_H_ADDR MT6685_DCXO_RGMON_CW0_H +#define XO_AUXOUT_SEL_H_MASK 0x3 +#define XO_AUXOUT_SEL_H_SHIFT 0 +#define XO_STATIC_AUXOUT_L_ADDR MT6685_DCXO_RGMON_CW2_L +#define XO_STATIC_AUXOUT_L_MASK 0xff +#define XO_STATIC_AUXOUT_L_SHIFT 0 +#define XO_STATIC_AUXOUT_H_ADDR MT6685_DCXO_RGMON_CW2_H +#define XO_STATIC_AUXOUT_H_MASK 0xff +#define XO_STATIC_AUXOUT_H_SHIFT 0 +#define XO_STATIC_AUXOUT_SEL_ADDR MT6685_DCXO_RGMON_CW1 +#define XO_STATIC_AUXOUT_SEL_MASK 0x7f +#define XO_STATIC_AUXOUT_SEL_SHIFT 0 +#define RG_XO_DIG26M_DIV2_ADDR MT6685_DCXO_DIGCLK_ELR +#define RG_XO_DIG26M_DIV2_MASK 0x1 +#define RG_XO_DIG26M_DIV2_SHIFT 0 +/* Register_LDO_REG*/ +#define RG_LDO_VBBCK_EN_ADDR MT6685_LDO_VBBCK_CON0 +#define RG_LDO_VBBCK_EN_MASK 0x1 +#define RG_LDO_VBBCK_EN_SHIFT 0 +#define RG_LDO_VBBCK_HW14_OP_EN_ADDR MT6685_LDO_VBBCK_OP_EN1 +#define RG_LDO_VBBCK_HW14_OP_EN_MASK 0x1 +#define RG_LDO_VBBCK_HW14_OP_EN_SHIFT 6 +#define RG_LDO_VRFCK1_EN_ADDR MT6685_LDO_VRFCK1_CON0 +#define RG_LDO_VRFCK1_EN_MASK 0x1 +#define RG_LDO_VRFCK1_EN_SHIFT 0 +#define RG_LDO_VRFCK1_HW14_OP_EN_ADDR MT6685_LDO_VRFCK1_OP_EN1 +#define RG_LDO_VRFCK1_HW14_OP_EN_MASK 0x1 +#define RG_LDO_VRFCK1_HW14_OP_EN_SHIFT 6 +#define RG_LDO_VRFCK2_EN_ADDR MT6685_LDO_VRFCK2_CON0 +#define RG_LDO_VRFCK2_EN_MASK 0x1 +#define RG_LDO_VRFCK2_EN_SHIFT 0 +#define RG_LDO_VRFCK2_HW14_OP_EN_ADDR MT6685_LDO_VRFCK2_OP_EN1 +#define RG_LDO_VRFCK2_HW14_OP_EN_MASK 0x1 +#define RG_LDO_VRFCK2_HW14_OP_EN_SHIFT 6 + + +/* Update PMIF base by platform if needed */ +#if !defined(PMIF_SPMI_P_BASE_CLKBUF) +#define PMIF_SPMI_P_BASE_CLKBUF 0x1C014000 +#endif /* !defined(PMIF_SPMI_P_BASE_CLKBUF) */ + +/* PMIF Register*/ +#define PMIFSPMI_INF_EN (PMIF_SPMI_BASE + 0x0024) +#define PMIFSPMI_INF_EN_SRCLKEN_RC_HW_MSK 0x1 +#define PMIFSPMI_INF_EN_SRCLKEN_RC_HW_SHFT 4 + +#define PMIFSPMI_OTHER_INF_EN (PMIF_SPMI_BASE + 0x0028) +#define SPMI_OTHER_INF_DCXO0_EN_MSK 0x1 +#define SPMI_OTHER_INF_DCXO0_EN_SHFT 0 +#define SPMI_OTHER_INF_DCXO1_EN_MSK 0x1 +#define SPMI_OTHER_INF_DCXO1_EN_SHFT 1 + +#define PMIFSPMI_ARB_EN (PMIF_SPMI_BASE + 0x0150) +#define PMIFSPMI_ARB_EN_SRCLKEN_RC_HW_MSK 0x1 +#define PMIFSPMI_ARB_EN_SRCLKEN_RC_HW_SHFT 4 +#define PMIFSPMI_ARB_EN_DCXO_CONN_MSK 0x1 +#define PMIFSPMI_ARB_EN_DCXO_CONN_SHFT 17 +#define PMIFSPMI_ARB_EN_DCXO_NFC_MSK 0x1 +#define PMIFSPMI_ARB_EN_DCXO_NFC_SHFT 18 + +#define PMIFSPMI_SLEEP_PROTECTION_CRL (PMIF_SPMI_BASE + 0x03F0) +#define PMIFSPMI_SPM_SLEEP_REQ_SEL_MSK 0x3 +#define PMIFSPMI_SPM_SLEEP_REQ_SEL_SHFT 0 +#define PMIFSPMI_SCP_SLEEP_REQ_SEL_MSK 0x3 +#define PMIFSPMI_SCP_SLEEP_REQ_SEL_SHFT 9 + +#define PMIFSPMI_MODE_CRL (PMIF_SPMI_BASE + 0x0408) +#define PMIFSPMI_MD_CTL_PMIF_RDY_MSK 0x1 +#define PMIFSPMI_MD_CTL_PMIF_RDY_SHFT 9 +#define PMIFSPMI_MD_CTL_SRCLK_EN_MSK 0x1 +#define PMIFSPMI_MD_CTL_SRCLK_EN_SHFT 10 +#define PMIFSPMI_MD_CTL_SRVOL_EN_MSK 0x1 +#define PMIFSPMI_MD_CTL_SRVOL_EN_SHFT 11 + +/* SPMI_P part */ +#define PMIFSPMI2_INF_EN (PMIF_SPMI_P_BASE_CLKBUF + 0x0024) +#define PMIFSPMI2_INF_EN_SRCLKEN_RC_HW_MSK 0x1 +#define PMIFSPMI2_INF_EN_SRCLKEN_RC_HW_SHFT 4 + +#define PMIFSPMI2_OTHER_INF_EN (PMIF_SPMI_P_BASE_CLKBUF + 0x0028) +#define SPMI2_OTHER_INF_DCXO0_EN_MSK 0x1 +#define SPMI2_OTHER_INF_DCXO0_EN_SHFT 0 +#define SPMI2_OTHER_INF_DCXO1_EN_MSK 0x1 +#define SPMI2_OTHER_INF_DCXO1_EN_SHFT 1 + +#define PMIFSPMI2_ARB_EN (PMIF_SPMI_P_BASE_CLKBUF + 0x0150) +#define PMIFSPMI2_ARB_EN_SRCLKEN_RC_HW_MSK 0x1 +#define PMIFSPMI2_ARB_EN_SRCLKEN_RC_HW_SHFT 4 +#define PMIFSPMI2_ARB_EN_DCXO_CONN_MSK 0x1 +#define PMIFSPMI2_ARB_EN_DCXO_CONN_SHFT 17 +#define PMIFSPMI2_ARB_EN_DCXO_NFC_MSK 0x1 +#define PMIFSPMI2_ARB_EN_DCXO_NFC_SHFT 18 + +#define PMIFSPMI2_SLEEP_PROTECTION_CRL (PMIF_SPMI_P_BASE_CLKBUF + 0x03F0) +#define PMIFSPMI2_SPM_SLEEP_REQ_SEL_MSK 0x3 +#define PMIFSPMI2_SPM_SLEEP_REQ_SEL_SHFT 0 +#define PMIFSPMI2_SCP_SLEEP_REQ_SEL_MSK 0x3 +#define PMIFSPMI2_SCP_SLEEP_REQ_SEL_SHFT 9 + +#define PMIFSPMI2_MODE_CRL (PMIF_SPMI_P_BASE_CLKBUF + 0x0408) +#define PMIFSPMI2_MD_CTL_PMIF_RDY_MSK 0x1 +#define PMIFSPMI2_MD_CTL_PMIF_RDY_SHFT 9 +#define PMIFSPMI2_MD_CTL_SRCLK_EN_MSK 0x1 +#define PMIFSPMI2_MD_CTL_SRCLK_EN_SHFT 10 +#define PMIFSPMI2_MD_CTL_SRVOL_EN_MSK 0x1 +#define PMIFSPMI2_MD_CTL_SRVOL_EN_SHFT 11 + +enum { + CLOCK_BUFFER_DISABLE, + CLOCK_BUFFER_SW_CONTROL, + CLOCK_BUFFER_HW_CONTROL +}; + +enum { + CLK_BUF_OUTPUT_IMPEDANCE_0, + CLK_BUF_OUTPUT_IMPEDANCE_1, + CLK_BUF_OUTPUT_IMPEDANCE_2, + CLK_BUF_OUTPUT_IMPEDANCE_3, + CLK_BUF_OUTPUT_IMPEDANCE_4, + CLK_BUF_OUTPUT_IMPEDANCE_5, + CLK_BUF_OUTPUT_IMPEDANCE_6, + CLK_BUF_OUTPUT_IMPEDANCE_7 +}; + +enum { + CLK_BUF_DRIVING_STRENGTH_0,/* Max */ + CLK_BUF_DRIVING_STRENGTH_1, + CLK_BUF_DRIVING_STRENGTH_2, + CLK_BUF_DRIVING_STRENGTH_3,/* Min */ +}; + +#define BBCK_BUF1_STATUS_PMIC CLOCK_BUFFER_HW_CONTROL +#define BBCK_BUF2_STATUS_PMIC CLOCK_BUFFER_HW_CONTROL +#define BBCK_BUF3_STATUS_PMIC CLOCK_BUFFER_DISABLE +#define BBCK_BUF4_STATUS_PMIC CLOCK_BUFFER_DISABLE +#define BBCK_BUF5_STATUS_PMIC CLOCK_BUFFER_DISABLE +#define RFCK_BUF1A_STATUS_PMIC CLOCK_BUFFER_DISABLE +#define RFCK_BUF1B_STATUS_PMIC CLOCK_BUFFER_HW_CONTROL +#define RFCK_BUF2A_STATUS_PMIC CLOCK_BUFFER_DISABLE +#define RFCK_BUF2B_STATUS_PMIC CLOCK_BUFFER_DISABLE + +#define BBCK_BUF1_OUTPUT_IMPEDANCE CLK_BUF_OUTPUT_IMPEDANCE_7 +#define BBCK_BUF2_OUTPUT_IMPEDANCE CLK_BUF_OUTPUT_IMPEDANCE_7 +#define BBCK_BUF3_OUTPUT_IMPEDANCE CLK_BUF_OUTPUT_IMPEDANCE_7 +#define BBCK_BUF4_OUTPUT_IMPEDANCE CLK_BUF_OUTPUT_IMPEDANCE_7 +#define BBCK_BUF5_OUTPUT_IMPEDANCE CLK_BUF_OUTPUT_IMPEDANCE_7 +#define RFCK_BUF1A_OUTPUT_IMPEDANCE CLK_BUF_OUTPUT_IMPEDANCE_1 +#define RFCK_BUF1B_OUTPUT_IMPEDANCE CLK_BUF_OUTPUT_IMPEDANCE_1 +#define RFCK_BUF2A_OUTPUT_IMPEDANCE CLK_BUF_OUTPUT_IMPEDANCE_1 +#define RFCK_BUF2B_OUTPUT_IMPEDANCE CLK_BUF_OUTPUT_IMPEDANCE_1 + +#define BBCK_BUF1_DRIVING_STRENGTH CLK_BUF_DRIVING_STRENGTH_2 +#define BBCK_BUF2_DRIVING_STRENGTH CLK_BUF_DRIVING_STRENGTH_2 +#define BBCK_BUF3_DRIVING_STRENGTH CLK_BUF_DRIVING_STRENGTH_2 +#define BBCK_BUF4_DRIVING_STRENGTH CLK_BUF_DRIVING_STRENGTH_2 +#define BBCK_BUF5_DRIVING_STRENGTH CLK_BUF_DRIVING_STRENGTH_2 + +enum pmic_interface_clkbuf { + PMIF_VLD_RDY_CLKBUF = 0, + PMIF_SLP_REQ_CLKBUF, + PMIF_MAX, +}; + +/* XO id: Update this enum for porting */ +enum xo_id { + XO_BBCK1 = 0, + XO_BBCK2, + XO_BBCK3, + XO_BBCK4, + XO_BBCK5, + XO_RFCK1A, + XO_RFCK1B, + XO_RFCK1C, + XO_RFCK2A, + XO_RFCK2B, + XO_RFCK2C, + XO_CONCK1, + XO_CONCK2, + XO_NUMBER, +}; + +struct ox_cfg { + u32 reg; + u8 mode; + u8 impedance; + u8 driving; + struct { + u8 low_byte; + u8 high_byte; + } voter_mask; +}; + +int clk_buf_init(void); +int clk_buf_set_default(void); +unsigned int clk_buf_get_pmrc_en0(void); +void pwrap_interface_init(void); + +#endif
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Jarried Lin (Code Review)