HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32492
Change subject: nb/x4x: Use system_reset() and full_reset() ......................................................................
nb/x4x: Use system_reset() and full_reset()
Use already defined system_reset() and full_reset() functions.
Change-Id: I0a05f3ac5c5340a509024de2b444960f498c3e99 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/x4x/raminit.c 1 file changed, 4 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/32492/1
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 4943428..4d5bdce 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -17,6 +17,7 @@ #include <arch/io.h> #include <device/pci_ops.h> #include <cbmem.h> +#include <cf9_reset.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> @@ -654,13 +655,11 @@ if (cache_not_found || (region_device_sz(&rdev) < sizeof(s))) { if (boot_path == BOOT_PATH_RESUME) { /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - halt(); + system_reset(); } else if (boot_path == BOOT_PATH_WARM_RESET) { /* On warm reset some of dram calibrations fail and therefore requiring valid cached settings */ - outb(0xe, 0xcf9); - halt(); + full_reset(); } ctrl_cached = NULL; } else { @@ -728,8 +727,7 @@ &s, sizeof(s)); if (s.boot_path == BOOT_PATH_RESUME && !cbmem_was_inited) { /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - halt(); + system_reset(); }
timestamp_add_now(TS_AFTER_INITRAM);
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32492 )
Change subject: nb/x4x: Use system_reset() and full_reset() ......................................................................
Patch Set 1: Code-Review+2
Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32492 )
Change subject: nb/x4x: Use system_reset() and full_reset() ......................................................................
nb/x4x: Use system_reset() and full_reset()
Use already defined system_reset() and full_reset() functions.
Change-Id: I0a05f3ac5c5340a509024de2b444960f498c3e99 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/32492 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M src/northbridge/intel/x4x/raminit.c 1 file changed, 4 insertions(+), 6 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 4943428..4d5bdce 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -17,6 +17,7 @@ #include <arch/io.h> #include <device/pci_ops.h> #include <cbmem.h> +#include <cf9_reset.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> @@ -654,13 +655,11 @@ if (cache_not_found || (region_device_sz(&rdev) < sizeof(s))) { if (boot_path == BOOT_PATH_RESUME) { /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - halt(); + system_reset(); } else if (boot_path == BOOT_PATH_WARM_RESET) { /* On warm reset some of dram calibrations fail and therefore requiring valid cached settings */ - outb(0xe, 0xcf9); - halt(); + full_reset(); } ctrl_cached = NULL; } else { @@ -728,8 +727,7 @@ &s, sizeof(s)); if (s.boot_path == BOOT_PATH_RESUME && !cbmem_was_inited) { /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - halt(); + system_reset(); }
timestamp_add_now(TS_AFTER_INITRAM);
-
HAOUAS Elyes (Code Review) -
Nico Huber (Code Review)