Change in coreboot[master]: mb/intel/tglrvp: Enable RTD3 for WWAN

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51315 )

Change subject: mb/intel/tglrvp: Enable RTD3 for WWAN
......................................................................

mb/intel/tglrvp: Enable RTD3 for WWAN

Enable the PCIe RTD3 driver for WWAN device attached to PCIe Root
Port 4 and provide the reset GPIO / src clk pin.

BUG=none
TEST=Boot to OS, verify the link is in L2 state during S0ix.

Change-Id: I669e02bd02e3af878648a6f3cf4fbb4d06c9857f
Signed-off-by: Bora Guvendik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51315
Tested-by: build bot (Jenkins) 
Reviewed-by: Lance Zhao
Reviewed-by: Wonkyu Kim 
---
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
2 files changed, 14 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Lance Zhao: Looks good to me, approved
  Wonkyu Kim: Looks good to me, approved

diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index 637afab..ce7c3d9 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -288,7 +288,13 @@
    	device pci 1c.0 off end # RP1			0xA0B8
    	device pci 1c.1 off end # RP2			0xA0B9
    	device pci 1c.2 on  end # RP3			0xA0BA
-		device pci 1c.3 on  end # RP4			0xA0BB
+		device pci 1c.3 on
+			chip soc/intel/common/block/pcie/rtd3
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B17)"
+				register "srcclk_pin" = "2"
+				device generic 0 on end
+			end
+		end # RP4					0xA0BB
    	device pci 1c.4 off end # RP5			0xA0BC
    	device pci 1c.5 off end # RP6			0xA0BD
    	device pci 1c.6 off end # RP7			0xA0BE
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index 83b924e..47ac01e 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -292,7 +292,13 @@
    	device pci 1c.0 off end # RP1			0xA0B8
    	device pci 1c.1 off end # RP2			0xA0B9
    	device pci 1c.2 on  end # RP3			0xA0BA
-		device pci 1c.3 on  end # RP4			0xA0BB
+		device pci 1c.3 on
+			chip soc/intel/common/block/pcie/rtd3
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B17)"
+				register "srcclk_pin" = "2"
+				device generic 0 on end
+			end
+		end # RP4					0xA0BB
    	device pci 1c.4 off end # RP5			0xA0BC
    	device pci 1c.5 off end # RP6			0xA0BD
    	device pci 1c.6 off end # RP7			0xA0BE