Change in coreboot[master]: soc/intel/cannonlake: Add PrmrrSize and C6DRAM config

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/21266

Change subject: soc/intel/cannonlake: Add PrmrrSize and C6DRAM config
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soc/intel/cannonlake: Add PrmrrSize and C6DRAM config

This patch ensures coreboot can set PRMRR size and C6DRAM
enable FSP-M UPDs.

Change-Id: I61ec3b6a16e20526516f681ddc3c70755724ed8a
Signed-off-by: Subrata Banik 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/romstage/romstage.c
2 files changed, 10 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/21266/1

diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 48305fe..0ed41fc 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -186,6 +186,14 @@

/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
    uint8_t eist_enable;
+	/* Enable C6 DRAM */
+	uint8_t enable_c6dram;
+	/*
+	 * PRMRR size setting with below options
+	 * 0x00100000 - 1MiB
+	 * 0x02000000 - 32MiB and beyond
+	 */
+	uint32_t PrmrrSize;
 };

typedef struct soc_intel_cannonlake_config config_t;
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 17c3191..5fa39ca 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -82,6 +82,8 @@
    		mask |= (1 << i);
    }
    m_cfg->PcieRpEnableMask = mask;
+	m_cfg->PrmrrSize = config->PrmrrSize;
+	m_cfg->EnableC6Dram = config->enable_c6dram;
 }

void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)