Change in coreboot[master]: HACK sc7180: bootblock/verstage/romstage need to zero bss HACK

[Julius Werner (Code Review)]

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35896 )

Change subject: HACK sc7180: bootblock/verstage/romstage need to zero bss HACK
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35896/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/35896/1//COMMIT_MSG@8 
PS1, Line 8:
> The verstage.c change allowed code to reach romstage.

Yeah, this is super weird. I can see plenty of reasons why BSS clearing for the bootblock might be broken, but for the verstage I have no idea how that might happen. I have a hunch that it might be a toolchain problem at this point, although I'm not really sure what toolchain would cause such a bad result.

When you run cbfstool print -v on the images it will show you more detailed output for stages, including the size in memory (the number behind the slash). Do you see a big difference between the same stages for the working and the broken images there? Like something might have dropped the BSS section from the ELF?